Espressif ESP32 Technical Reference Manual page 715

31 Low-Power Management (RTC_CNTL)
31
0 0 0 0 0 0 0
RTC_CNTL_MAIN_TIMER_INT_CLR Set this bit to clear the RTC_CNTL_MAIN_TIMER_INT interrupt.
(WO)
RTC_CNTL_BROWN_OUT_INT_CLR Set this bit to clear the RTC_CNTL_BROWN_OUT_INT interrupt.
(WO)
RTC_CNTL_TOUCH_INT_CLR Set this bit to clear the RTC_CNTL_TOUCH_INT interrupt. (WO)
RTC_CNTL_SAR_INT_CLR Set this bit to clear the RTC_CNTL_SAR_INT interrupt. (WO)
RTC_CNTL_TIME_VALID_INT_CLR Set this bit to clear the RTC_CNTL_TIME_VALID_INT interrupt.
(WO)
RTC_CNTL_WDT_INT_CLR Set this bit to clear the RTC_CNTL_WDT_INT interrupt. (WO)
RTC_CNTL_SDIO_IDLE_INT_CLR Set this bit to clear the RTC_CNTL_SDIO_IDLE_INT interrupt.
(WO)
RTC_CNTL_SLP_REJECT_INT_CLR Set this bit to clear the RTC_CNTL_SLP_REJECT_INT interrupt.
(WO)
RTC_CNTL_SLP_WAKEUP_INT_CLR Set this bit to clear the RTC_CNTL_SLP_WAKEUP_INT interrupt.
(WO)
Register 31.18. RTC_CNTL_STOREn_REG (n: 0-3) (0x004C+4*n)
31
x x x x x x x
RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W)
Espressif Systems
Register 31.17. RTC_CNTL_INT_CLR_REG (0x0048)
0 0 0 0 0 0 0 0
x x x x x x x x
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9 8
0 0 0 0 0 0 0 0 0
x x x x x x x x
715
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
x x x x x x x x
ESP32 TRM (Version 5.2)
Reset
0
x Reset