Espressif ESP32 Technical Reference Manual page 389

13 UART Controller (UART)
31
0 0 0 0 0 0 0
UHCI_RXFIFO_TIMEOUT_ENA This is the enable bit for DMA send-data timeout. (R/W)
UHCI_RXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value is equal to or greater than
(17'd8000»reg_rxfifo_timeout_shift). (R/W)
UHCI_RXFIFO_TIMEOUT This register stores the timeout value. When DMA takes more time to read
data from RAM than what this register indicates, it will produce the UHCI_RX_HUNG_INT interrupt.
(R/W)
UHCI_TXFIFO_TIMEOUT_ENA The enable bit for Tx FIFO receive-data timeout (R/W)
UHCI_TXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value is equal to or greater than
(17'd8000»reg_txfifo_timeout_shift). (R/W)
UHCI_TXFIFO_TIMEOUT This register stores the timeout value. When DMA takes more time to re-
ceive data than what this register indicates, it will produce the UHCI_TX_HUNG_INT interrupt.
(R/W)
31
0 0 0 0 0 0 0
UHCI_ESC_SEQ2_CHAR1 This register stores the second char used to replace the reg_esc_seq2
in data. (R/W)
UHCI_ESC_SEQ2_CHAR0 This register stores the first char used to replace the reg_esc_seq2 in
data. (R/W)
UHCI_ESC_SEQ2 This register stores the flow_control char to turn off the flow_control. (R/W)
Espressif Systems
Register 13.51. UHCI_HUNG_CONF_REG (0x68)
24 23 22 20 19
0 1 0 0 0
Register 13.52. UHCI_ESC_CONFn_REG (n: 0-3) (0xB0+4*n)
24 23
0 0x0DF
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12 11 10
0x010 1 0 0
16 15
0x0DB
389
8 7
0 0x010
8 7
0x013
ESP32 TRM (Version 5.2)
0
Reset
0
Reset