Espressif ESP32 Technical Reference Manual page 679

30 ULP Coprocessor (ULP)
30.6.2.4 Connecting I²C Signals
SDA and SCL signals can be mapped onto two out of the four GPIO pins, which are identified in Table
RTC_MUX Pin Summary
register.
30.7 Register Summary
30.7.1 SENS_ULP Address Space
Name
ULP Timer cycles select
SENS_ULP_CP_SLEEP_CYC0_REG
SENS_ULP_CP_SLEEP_CYC1_REG
SENS_ULP_CP_SLEEP_CYC2_REG
SENS_ULP_CP_SLEEP_CYC3_REG
SENS_ULP_CP_SLEEP_CYC4_REG
RTC I2C slave address select
SENS_SAR_SLAVE_ADDR1_REG
SENS_SAR_SLAVE_ADDR2_REG
SENS_SAR_SLAVE_ADDR3_REG
SENS_SAR_SLAVE_ADDR4_REG
RTC I²C control
SENS_SAR_I2C_CTRL_REG
30.7.2 RTC_I2C Address Space
Name
RTC I²C control registers
RTC_I2C_CTRL_REG
RTC_I2C_DEBUG_STATUS_REG
RTC_I2C_TIMEOUT_REG
RTC_I2C_SLAVE_ADDR_REG
RTC I2C signal setting registers
RTC_I2C_SDA_DUTY_REG
RTC_I2C_SCL_LOW_PERIOD_REG
RTC_I2C_SCL_HIGH_PERIOD_REG
RTC_I2C_SCL_START_PERIOD_REG
RTC_I2C_SCL_STOP_PERIOD_REG
RTC I²C interrupt registers - listed only for debugging
RTC_I2C_INT_CLR_REG
RTC_I2C_INT_EN_REG
Espressif Systems
in Chapter IO_MUX and GPIO
Description
Timer cycles setting 0
Timer cycles setting 1
Timer cycles setting 2
Timer cycles setting 3
Timer cycles setting 4
I²C addresses 0 and 1
I²C addresses 2 and 3
I²C addresses 4 and 5
I²C addresses 6 and 7, I2C control
I²C control registers
Description
Transmission setting
Debug status
Timeout setting
Local slave address setting
Configures the SDA hold time after a neg-
ative SCL edge
Configures the low level width of SCL
Configures the high level width of SCL
Configures the delay between the SDA and
SCL negative edge for a start condition
Configures the delay between the SDA and
SCL positive edge for a stop condition
Clear status of I²C communication events
Enable capture of I²C communication sta-
tus events
Submit Documentation Feedback
Matrix, using the RTCIO_SAR_I2C_IO_REG
679
Address Access
0x3FF48818 R/W
0x3FF4881C R/W
0x3FF48820 R/W
0x3FF48824 R/W
0x3FF48828 R/W
0x3FF4883C R/W
0x3FF48840 R/W
0x3FF48844 R/W
0x3FF48848 R/W
0x3FF48850 R/W
Address Access
0x3FF48C04 R/W
0x3FF48C08 R/W
0x3FF48C0C R/W
0x3FF48C10 R/W
0x3FF48C30 R/W
0x3FF48C00 R/W
0x3FF48C38 R/W
0x3FF48C40 R/W
0x3FF48C44 R/W
0x3FF48C24 R/W
0x3FF48C28 R/W
ESP32 TRM (Version 5.2)