Espressif ESP32 Technical Reference Manual page 384

13 UART Controller (UART)
31
0 0 0 0 0 0 0
UHCI_OUT_EMPTY 1: DMA inlink descriptor's FIFO is empty. (RO)
UHCI_OUT_FULL 1: DMA outlink descriptor's FIFO is full. (RO)
31
0 0 0 0 0 0 0
UHCI_OUTFIFO_PUSH Set this bit to push data into DMA FIFO. (R/W)
UHCI_OUTFIFO_WDATA This is the data that need to be pushed into DMA FIFO. (R/W)
31
0 0 0 0 0 0 0
UHCI_INFIFO_POP Set this bit to pop data from DMA FIFO. (R/W)
UHCI_INFIFO_RDATA This register stores the data popping from DMA FIFO. (RO)
Espressif Systems
Register 13.34. UHCI_DMA_OUT_STATUS_REG (0x14)
0 0 0 0 0 0 0 0
Register 13.35. UHCI_DMA_OUT_PUSH_REG (0x18)
17
0 0 0 0 0 0 0 0
Register 13.36. UHCI_DMA_IN_POP_REG (0x20)
17
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
16 15 9
0 0 0 0 0 0 0 0
16 15 12 11
0 0 0 0 0
384
2 1
0 0 0 0 0 0 0 1
8
0x000
0x0000
ESP32 TRM (Version 5.2)
0
0
Reset
0
Reset
0
Reset