Espressif ESP32 Technical Reference Manual page 623

27 Memory Management and Protection Units (MMU, MPU)
VAddr Count
L
128
V Addr
RAM
R
128
V Addr
RAM
Examples
Example 1. A PRO_CPU process, with a PID of 7, needs to read or write external RAM address 0x7F_A375 via
virtual address 0x3FA7_2375. The MMU is in Low-High mode.
• According to Table 27-9, virtual address 0x3FA7_2375 resides in the 0x4E'th 32-KB-page of V Addr
• According to Table 27-16, virtual address 0x3FA7_2375 is governed by
• According to Table 27-18, the MMU entry for
• The modified MMU entry is 3968 + 0x4E = 4046.
• Address 0x7F_A375 resides in the 255'th 32 KB-sized page.
• MMU entry 4046 needs to be set to 255 and marked as valid by clearing the 8'th bit. Thus, 0x0FF is
written to MMU entry 4046.
Example 2. An APP_CPU process, with a PID of 5, needs to read or write external RAM address 0x55_5805 up
to 0x55_5823 starting at virtual address 0x3F85_5805. The MMU is in Even-Odd mode.
• According to Table 27-9, virtual address 0x3F85_5805 resides in the 0x0A'th 32-KB-page of V Addr
• According to Table 27-17, the range to be read/written spans both a 32-byte region in
L
.
V Addr
RAM
• According to Table 27-18, the MMU entry for
• According to Table 27-18, the MMU entry for
• The modified MMU entries are 1664 + 0x0A = 1674 and 3712 + 0x0A = 3722.
• The addresses 0x55_5805 to 0x55_5823 reside in the 0xAA'th 32 KB-sized page.
• MMU entries 1674 and 3722 need to be set to 0xAA and marked as valid by setting the 8'th bit to 0. Thus,
0x0AA is written to MMU entries 1674 and 3722. This mapping applies to both the PRO_CPU and the
APP_CPU.
Example 3. A PRO_CPU process, with a PID of 1, and an APP_CPU process whose PID is also 1, need to read
or write external RAM using virtual address 0x3F80_0876. The PRO_CPU needs this region to access physi-
cal address 0x10_0876, while the APP_CPU wants to access physical address 0x20_0876 through this virtual
address. The MMU is in Normal mode.
• According to Table 27-9, virtual address 0x3F80_0876 resides in the 0'th 32-KB-page of V Addr
• According to Table 27-18, the MMU entry for PID 1 for the PRO_CPU starts at 1152.
• According to Table 27-18, the MMU entry for PID 1 for the APP_CPU starts at 3200.
• The MMU entries that are modified are 1152 + 0 = 1152 for the PRO_CPU and 3200 + 0 = 3200 for the
APP_CPU.
• Address 0x10_0876 resides in the 0x20'th 32 KB-sized page.
• Address 0x20_0876 resides in the 0x40'th 32 KB-sized page.
• For the PRO_CPU, MMU entry 1152 needs to be set to 0x20 and marked as valid by clearing the 8'th bit.
Thus, 0x020 is written to MMU entry 1152.
Espressif Systems
Table 27-18. MMU Entry Numbers for External RAM
0/1 2
1152 1280
3200 3328
R
V Addr
L
V Addr
R
V Addr
623
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First MMU entry for PID
3 4 5
1408 1536 1664
3456 3584 3712
R
V Addr
for PID 7 for the PRO_CPU starts at 3968.
RAM
for PID 5 starts at 1664.
RAM
for PID 5 starts at 3712.
RAM
6 7
1792 1920
3840 3968
RAM
.
RAM
RAM
R
and
V Addr
RAM
.
RAM
ESP32 TRM (Version 5.2)
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