Espressif ESP32 Technical Reference Manual page 739

Revision History
Date Version Release notes
Added Section: Documentation Conventions
Changes to Chapter
Changes to Chapter
Changes to Chapter
Changes to Chapter I²S:
Changes to Chapter
2020.06 V4.2
Changes to Chapter LED_PWM:
Changes to Chapter MCPWM:
Changes to Chapter PULSE_CNT:
Changes to Chapter
Changes to Chapter
Changes to Chapter
Espressif Systems
Cont'd from previous page
System and
• Added a note about DPORT address and AHB address under Table
Reset and
• Updated Table
3-3 by adding PLL_CLK frequency of 480 MHz and CPU_CLK fre-
quency of 240 MHz
• Updated Table
3-5 by modifying the APB_CLK frequency to 80 MHz when the
CPU_CLK source is PLL_CLK
IO_MUX and GPIO
• Fixed a typo in Section 4.4.2: For inputs, the SIG_IN_SEL register must be cleared
to route the input directly to the peripheral.
• Changed the reset values for MTCK, MTMS, GPIO27 in Table
• Updated description of register
• Updated Section
12.4.1.1
UART Controllers:
• Updated the description of registers
• Added Table
14-1
• Corrected the PWM period in Count-Up, Count-Down, and Count-Up-Down modes
• Added description of register
eFuse Controller:
• Combined system parameters "32pad" and "chip_version" into one: pkg_version
• Updated
description
EFUSE_CHIP_VER_PKG
Low-Power
• Added description of register
• Modified description of register
ULP Coprocessor:
• Updated description in sections
• Fixed typos
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Memory:
Clock:
Matrix:
FUN_DRV
UART_FIFO_REG
PCNT_Un_STATUS_REG
of registers EFUSE_RD_CHIP_VER_PKG
Management:
RTC_CNTL_WDTCONFIG0_REG
RTC_CNTL_WDTCONFIGn_REG
30.4.13 and 30.4.14
739
1-6
4-3
and UART_RX_TOUT_THRHD
Cont'd on next page
ESP32 TRM (Version 5.2)
and