Espressif ESP32 Technical Reference Manual page 103

5 DPort Registers
5.5 Registers
The addresses in parenthesis besides register names are the register addresses relative to the DPORT base
address provided in Table
register addresses are listed in Section
Register 5.1. DPORT_PRO_BOOT_REMAP_CTRL_REG (0x000)
31
0 0 0 0 0 0 0
DPORT_PRO_BOOT_REMAP Remap mode for PRO_CPU. (R/W)
Register 5.2. DPORT_APP_BOOT_REMAP_CTRL_REG (0x004)
31
0 0 0 0 0 0 0
DPORT_APP_BOOT_REMAP Remap mode for APP_CPU. (R/W)
31
0 0 0 0 0 0 0
DPORT_PERI_EN_RSA Set the bit to enable the clock of RSA module. Clear the bit to disable the
clock of RSA module. (R/W)
DPORT_PERI_EN_SHA Set the bit to enable the clock of SHA module. Clear the bit to disable the
clock of SHA module. (R/W)
DPORT_PERI_EN_AES Set the bit to enable the clock of AES module. Clear the bit to disable the
clock of AES module. (R/W)
Espressif Systems
1-6 Peripheral Address Mapping in Chapter
5.4 Register
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Register 5.3. DPORT_PERI_CLK_EN_REG (0x01C)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
103
Memory. The absolute
0 0 0 0 0 0 0
0 0 0 0 0 0 0
3 2
0 0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
1 0
0 0
Reset
1 0
0 0 Reset
1 0
0 Reset