Espressif ESP32 Technical Reference Manual page 612

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27 Memory Management and Protection Units (MMU, MPU)

The decision an MPU can make, based on this information, is to allow or deny a process to access the memory

region or peripheral. An MMU has the same function, but additionally it redirects the virtual memory access,

which the process acquired, into a physical memory access that can possibly reach out an entirely different

physical memory region. This way, MMU-governed memory can be remapped on a process-by-process ba-

27.3.2.1 Embedded Memory

The on-chip memory is governed by fixed-function MPUs, configurable MPUs, and MMUs:

SRAM1 (aliases)

RTC FAST (aliases)

ROM0, ROM1, the lower 64 KB of SRAM0, SRAM1 and the lower 72 KB of SRAM2 are governed by a static MPU.

The behaviour of these MPUs are hardwired and cannot be configured by software. They moderate access to

the memory region solely through the PID of the current process. When the PID of the process is 0 or 1, the

memory can be read (and written when it is RAM) using the addresses specified in Table 27-1. When it is 2 ~ 7,

the memory cannot be accessed.

RTC FAST & RTC SLOW MPU

The 8 KB RTC FAST Memory as well as the 8 KB of RTC SLOW Memory are governed by two configurable MPUs.

The MPUs can be configured to allow or deny access to each individual PID, using the RTC_CNTL_RTC_PID_

CONFIG_REG and DPORT_AHBLITE_MPU_TABLE_RTC_REG registers. Setting a bit in these registers will allow

the corresponding PID to read or write from the memory; clearing the bit disallows access. Access for PID 0 and

1 to RTC SLOW memory cannot be configured and is always enabled. Table

mappings of the registers.

Espressif Systems

Table 27-1. MPU and MMU Structure for Internal Memory

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Address range

RTC FAST MPU

RTC SLOW MPU

define the bit-to-PID

ESP32 TRM (Version 5.2)

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