Espressif ESP32 Technical Reference Manual page 142

7 SPI Controller (SPI)
31 30
1 0 0 0 0 0 0
SPI_CLK_EQU_SYSCLK In master mode, when this bit is set to 1, SPI output clock is equal to system
clock; when set to 0, SPI output clock is divided from system clock. In slave mode, it should be
set to 0. (R/W)
SPI_CLKDIV_PRE In master mode, it is used to configure the pre-divider value for SPI output clock.
It is only valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)
SPI_CLKCNT_N In master mode, it is used to configure the divider for SPI output clock. It is only
valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)
SPI_CLKCNT_H In master mode, SPI_CLKCNT_H = ⌊
SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)
SPI_CLKCNT_L In master mode, it is equal to SPI_CLKCNT_N. It is only valid when
SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)
Espressif Systems
Register 7.7. SPI_CLOCK_REG (0x18)
18 17
0 0 0 0 0 0 0
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12 11
0x03 0x01
SPI_CLKCNT_N+1
–1⌋.
2
142
6 5 0
0x03
Reset
It is only valid when
ESP32 TRM (Version 5.2)