Espressif ESP32 Technical Reference Manual page 742

Revision History
Date Version Release notes
Updated Figure
2018.04 V3.1 Added a note to Section 4.7;
Added the function description for the bits of the register in Section 4.46.
Updated the
2018.03 V3.0 Added description of registers
tion
Updated Sections 4.2.2, 4.2.3, 4.3.2;
2018.02 V2.9
Added registers I2S_FIFO_WR_REG and I2S_FIFO_RD_REG in Section
2018.01 V2.8 Added Chapter
Added the description of system parameter
troller.
Added Subsection
2017.12 V2.7 Updated Section
Updated the description of
Updated Chapter
2017.11 V2.6
Added notes in Section
Updated the addresses for register SPI_CTRL_REG in Section
Added Section
2017.11 V2.5 scription of register CLK_EDGE_SEL;
Major revision on Chapter
Added the description of register
Added notes in Section
Added a note in Section GP-SPI Master Mode;
2017.09 V2.4
Added Chapter
Added Chapter
2017.08 V2.3 Added Chapter
2017.07 V2.2 Added Chapter
Updated the addresses of the GPIO configuration/data registers and the GPIO RTC func-
tion configuration registers in Chapter
2017.07 V2.1
Added Chapter
2017.07 V2.0 Added Chapter
Updated Chapter
2017.06 V1.9
Added Chapter MCPWM.
Added register
2017.06 V1.8 Updated Chapter
Added Chapter
Added Chapter
Added Section
2017.05 V1.7 Updated Section
Espressif Systems
Cont'd from previous page
15-1 RMT Architecture;
instruction layout diagram of ST
10.9 and Section 10.10.
Ethernet MAC.
Cache in Section
Timers and the naming of several registers in LED_PWM;
Remote Controller
• Updated Figure
15-1 RMT Architecture;
• Updated section
RMT
• Updated section Transmitter;
• Updated the description of RMT_CHn_TX_THR_EVENT_INT.
UART RAM
Clock Phase Selection
I2C
The Clock of I2S
DPort Register;
DMA Controller.
Flash Encryption/Decryption.
Low-Power Management.
PID Controller.
SDIO Slave.
IO_MUX and GPIO
I2S_STATE_REG
IO_MUX and GPIO
ULP Coprocessor.
On-Chip Sensors and Analog Signal
Audio PLL;
eFuse Controller Register
Submit Documentation Feedback
in Section 30.4.2;
EMACADDR2HIGH_REG
BLK3_part_reserve
System and Memory;
console_debug_disable
Peripheral:
RAM;
and Register UART_CONF0_REG.
in Chapter SD/MMC Host Controller, and a de-
Controller.
SLC0HOST_TOKEN_RDATA
Module;
IO_MUX and GPIO
Matrix;
in Chapter I2S;
Matrix;
Processing;
Summary;
742
to EMACADDR7LOW_REG
I2S Registers.
in Chapter eFuse Con-
in Chapter eFuse Controller.
SPI Register Summary;
in Chapter SDIO
Matrix;
Cont'd on next page
ESP32 TRM (Version 5.2)
in Sec-
Slave;