Espressif ESP32 Technical Reference Manual page 651

29 On-Chip Sensors and Analog Signal Processing
29.6 Registers
29.6.1 Sensors
The addresses in parenthesis besides register names are the register addresses relative to (the RTC base ad-
dress + 0x0800). The RTC base address is provided in Table
System and Memory. The absolute register addresses are listed in Section
31 29 28 27 26
0 0 0 0 0 0 0
SENS_SAR1_DATA_INV Invert SAR ADC1 data. (R/W)
SENS_SAR1_DIG_FORCE 1: SAR ADC1 controlled by DIG ADC1 CTR, 0: SAR ADC1 controlled by RTC
ADC1 CTRL. (R/W)
SENS_SAR1_SAMPLE_BIT Bit width of SAR ADC1, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11: for
12-bit. (R/W)
SENS_SAR1_SAMPLE_CYCLE Sample cycles for SAR ADC1. (R/W)
SENS_SAR1_CLK_DIV Clock divider. (R/W)
31
SENS_ULP_CP_SLEEP_CYC0_REG Sleep cycles for ULP coprocessor timer. (R/W)
Espressif Systems
Register 29.1. SENS_SAR_READ_CTRL_REG (0x0000)
18 17
0 0 0 0 0 0 0 3
Register 29.2. SENS_ULP_CP_SLEEP_CYC0_REG (0x0018)
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1-6 Peripheral Address Mapping in Chapter
16 15
9
200
651
29.5.1 Sensors.
8 7
2
ESP32 TRM (Version 5.2)
1
0
Reset
0
Reset