Espressif ESP32 Technical Reference Manual page 19

List of Figures
List of Figures
1-1 System Structure
1-2 System Address Mapping
1-3 Cache Block Diagram
2-1 Interrupt Matrix Structure
3-1 System Reset
3-2 System Clock
4-1 IO_MUX, RTC IO_MUX and GPIO Matrix Overview
4-2 Peripheral Input via IO_MUX, GPIO Matrix
4-3 Output via GPIO Matrix
4-4 ESP32 I/O Pad Power Sources (QFN 6*6, Top View)
4-5 ESP32 I/O Pad Power Sources (QFN 5*5, Top View)
6-1 DMA Engine Architecture
6-2 Linked List Structure
6-3 Data Transfer in UDMA Mode
6-4 SPI DMA
7-1 SPI Architecture
7-2 SPI Master and Slave Full-duplex/Half-duplex Communication
7-3 SPI Data Buffer
7-4 GP-SPI
7-5 Parallel QSPI
7-6 Communication Format of Parallel QSPI
8-1 SDIO Slave Block Diagram
8-2 SDIO Bus Packet Transmission
8-3 CMD53 Content
8-4 SDIO Slave DMA Linked List Structure
8-5 SDIO Slave Linked List
8-6 Packet Sending Procedure (Initiated by Slave)
8-7 Packet Receiving Procedure (Initiated by Host)
8-8 Loading Receiving Buffer
8-9 Sampling Timing Diagram
8-10 Output Timing Diagram
9-1 SD/MMC Controller Topology
9-2 SD/MMC Controller External Interface Signals
9-3 SDIO Host Block Diagram
9-4 Command Path State Machine
9-5 Data Transmit State Machine
9-6 Data Receive State Machine
9-7 Descriptor Chain
9-8 The Structure of a Linked List
9-9 SD/MMC Timing in HS Mode
9-10 Clock Phase Selection
10-1 Ethernet MAC Functionality Overview
10-2 Ethernet Block Diagram
Espressif Systems 19
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ESP32 TRM (Version 5.2)