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Espressif ESP32 Manuals
Manuals and User Guides for Espressif ESP32. We have
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Espressif ESP32 manuals available for free PDF download: Technical Reference Manual, At Instruction Set, Manual, User Manual
Espressif ESP32 Technical Reference Manual (744 pages)
Brand:
Espressif
| Category:
Single board computers
| Size: 10 MB
Table of Contents
About this Manual
2
Document Updates
2
Revision History
2
Table of Contents
16
List of Tables
16
List of Figures
19
Functional Description
26
Embedded Memory
26
Address Mapping
26
Embedded Memory Address Mapping
28
External Memory
30
Module with DMA
30
External Memory Address Mapping
30
Peripheral Address Mapping
32
Memory Speed
34
Interrupt Matrix Structure
35
CPU Interrupts
38
Reset Source
40
System Reset
40
PRO_CPU and APP_CPU Reset Reason Values
40
System Clock
41
Clock Source
42
CPU Clock
42
CPU_CLK Derivation
42
Peripheral Clock Usage
43
CPU_CLK Source
44
Apb_Clk
44
Ref_Tick
44
RTC Clock
45
Register Summary
45
Peripheral Input Via IO_MUX, GPIO Matrix
50
ESP32 I/O Pad Power Sources (QFN 6*6, Top View)
55
ESP32 I/O Pad Power Sources (QFN 5*5, Top View)
56
IO_MUX Pad Summary
61
RTC_MUX Pin Summary
62
Register Summary
63
Functional Description
94
Register Summary
96
DMA Controller (DMA)
122
Functional Description
122
DMA Engine Architecture
122
Spi Dma
125
SPI Architecture
127
SPI Features
128
SPI Master and Slave Full-Duplex/Half-Duplex Communication
128
SPI Data Buffer
130
Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master
131
Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave
131
Gp-Spi
133
Parallel QSPI
133
SPI Interrupts
134
DMA Interrupts
134
Communication Format of Parallel QSPI
134
Register Summary
135
Functional Description
161
SDIO Slave Block Diagram
161
Register Access
162
CMD53 Content
162
Register Summary
168
SD/MMC Controller Topology
194
SD/MMC Controller External Interface Signals
195
Functional Description
195
Descriptor Chain
200
The Structure of a Linked List
201
Clock Phase Selection
205
Register Summary
206
Transmit Operation
228
Ethernet Block Diagram
228
Error Handling
231
MAC Address Filtering
232
Destination Address Filtering
233
Source Address Filtering
233
PHY Interface
234
MII Interface
235
MII Clock
236
RMII Interface
237
Timing Parameters - Receiving Data
238
RMII Clock
238
RMII Timing - Receiving Data
238
Timing Parameters - Transmitting Data
239
Transmit Descriptor
239
Transmit Descriptor 0 (TDES0)
240
Receive Descriptors
244
Transmit Descriptor 1 (TDES1)
244
Transmit Descriptor 2 (TDES2)
244
Transmit Descriptor 3 (TDES3)
244
Receive Descriptor 0 (RDES0)
245
Receive Descriptor
245
Receive Descriptor 1 (RDES1)
247
Receive Descriptor 2 (RDES2)
248
Receive Descriptor 3 (RDES3)
248
Receive Descriptor 4 (RDES4)
248
Register Summary
249
Functional Description
289
I2C Master Architecture
290
I2C Slave Architecture
290
I2C Bus Timing
291
I2C Sequence Chart
291
SCL Frequency Configuration
291
Structure of the I2C Command Register
292
I2C Master Writes to Slave with 7-Bit Address
293
I2C Master Writes to Slave with 10-Bit Address
294
I2C Master Writes to Addrm in RAM of Slave with 7-Bit Address
295
Master Writes to Slave with 7-Bit Address in Three Segments
296
Master Reads from Slave with 7-Bit Address
297
Master Reads from Slave with 10-Bit Address
298
Master Reads N Bytes of Data from Addrm in Slave with 7-Bit Address
298
Master Reads from Slave with 7-Bit Address in Three Segments
299
Register Summary
300
I2S System Block Diagram
313
I2S Signal Bus Description
314
I2S Clock
315
Philips Standard
316
Module Reset
317
FIFO Operation
317
MSB Alignment Standard
317
PCM Standard
317
Sending Data
318
Register Configuration
318
Receiving Data
319
Modes of Writing Received Data into FIFO and the Corresponding Register Configuration
320
Modes of Writing Received Data into FIFO
320
PDM Sends Signal
323
PDM Receives Signal
323
PDM Receive Module
323
LCD Master Transmitting Mode
324
LCD Master Transmitting Data Frame, Form
324
Camera Slave Receiving Mode
325
ADC Interface of I2S0
325
DAC Interface of I2S
326
Data Input by I2S DAC Interface
326
Register Summary
327
Functional Description
347
UART Basic Structure
348
UART Shared RAM
349
Flow Control
351
AT_CMD Character Format
351
Software Flow Control
352
Hardware Flow Control
352
UART Interrupts
353
Register Summary
354
UART Registers
358
LED_PWM Architecture
390
Commonly-Used Frequencies and Resolutions
392
Register Summary
394
Functional Description
408
RMT Architecture
408
Data Structure
409
Register Summary
410
MCPWM Module Overview
417
Prescaler Submodule
419
Timer Submodule
419
Operator Submodule
420
Configuration Parameters of the Operator Submodule
421
Fault Detection Submodule
422
Capture Submodule
422
Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event
424
Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event
424
UTEP and UTEZ Generation in Count-Up Mode
425
DTEP and DTEZ Generation in Count-Down Mode
426
DTEP and UTEZ Generation in Count-Up-Down Mode
426
Submodules Inside the PWM Operator
429
Timing Events Priority When PWM Timer Increments
431
Timing Events Priority When PWM Timer Decrements
431
Symmetrical Waveform in Count-Up-Down Mode
433
Pwmxb - Active High
434
Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on Pwmxa
435
Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on Pwmxa and Pwmxb - Active High
436
Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on Pwmxa and Pwmxb - Complementary
437
Example of an NCI Software-Force Event on Pwmxa
438
Example of a CNTU Software-Force Event on Pwmxb
439
Dead Time Generator Switches Control Registers
441
Options for Setting up the Dead Time Generator Submodule
441
Active High Complementary (AHC) Dead Time Waveforms
442
Active Low Complementary (ALC) Dead Time Waveforms
443
Active High (AH) Dead Time Waveforms
443
Active Low (AL) Dead Time Waveforms
444
Example of Waveforms Showing PWM Carrier Action
446
Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule
448
Register Summary
451
Functional Description
501
PULSE_CNT Architecture
501
ESP32 TRM (Version 5.2)
501
Register Summary
504
Alarm Generation
512
Write Protection
522
System Parameters
523
BLOCK1/2/3 Encoding
526
Programming of System Parameters
527
Program Registers
527
Timing Configuration
529
Software Read Registers
530
Register Summary
531
The Bit Fields of Data Frames and Remote Frames
547
Data Frames and Remote Frames in SFF and EFF
548
Error Frame
549
Overload Frame
550
The Bit Fields of an Overload Frame
550
Interframe Space
551
Error States
552
Error Counters
552
Architectural Overview
554
Layout of a Bit
555
Functional Description
557
Bit Timing
558
Bit Information of TWAI_CLOCK_DIVIDER_REG; TWAI Address 0X18
558
Bit Information of TWAI_BUS_TIMING_1_REG; TWAI Address 0X1C
558
Interrupt Management
558
Frame Information
561
TX/RX Frame Information (SFF/EFF); TWAI Address 0X40
561
TX/RX Identifier 1 (SFF); TWAI Address 0X44
562
TX/RX Identifier 2 (SFF); TWAI Address 0X48
562
TX/RX Identifier 1 (EFF); TWAI Address 0X44
562
TX/RX Identifier 2 (EFF); TWAI Address 0X48
562
TX/RX Identifier 3 (EFF); TWAI Address 0X4C
562
TX/RX Identifier 4 (EFF); TWAI Address 0X50
562
Acceptance Filter
563
Single Filter Mode
564
Error Management
565
Dual Filter Mode
565
Error State Transition
566
Bit Information of TWAI_ERR_CODE_CAP_REG; TWAI Address 0X30
567
Bit Information of Bits SEG.4 - SEG.0
567
Register Summary
568
Twai_Cmd_Reg
569
Positions of Arbitration Lost Bits
570
Twai_Tx_Req
578
Twai_Self_Rx_Req
578
Twai_Abort_Tx
578
Twai_Release_Buf
578
Functional Description
583
Key Endianness
583
Operation Mode
583
AES Text Endianness
584
Register Summary
586
Random Number Generator (Rng)
604
Noise Source
604
Programming Procedure
605
Flash Encryption/Decryption Module Architecture
606
Key Generator
607
PID Controller
611
MPU and MMU Structure for Internal Memory
612
MMU Access Example
614
Page Boundaries for SRAM0 MMU
615
Page Boundaries for SRAM2 MMU
615
MPU for DMA
617
Virtual Address for External Memory
619
MMU Entry Numbers for PRO_CPU
620
MMU Entry Numbers for APP_CPU
620
Virtual Address Mode for External SRAM
621
Virtual Address for External SRAM ( Normal Mode )
622
Virtual Address for External SRAM ( Low-High Mode )
622
Virtual Address for External SRAM (Even-Odd Mode)
622
MMU Entry Numbers for External RAM
623
MPU for Peripheral
624
Functional Description
626
Interrupt Vector Entry Address
627
Register Summary
631
Touch Sensor
637
ESP32 Capacitive Sensing Touch Pads
638
Touch Sensor Structure
638
Touch Sensor Operating Flow
639
Touch FSM Structure
640
Outline of Function
641
SAR ADC Depiction
641
SAR ADC Outline of Function
642
Inputs of SAR ADC
643
ESP32 SAR ADC Controllers
643
RTC SAR ADC Outline of Function
644
Fields of the Pattern Table Register
645
Diagram of DIG SAR ADC Controllers
645
Fields of Type I DMA Data Format
646
Fields of Type II DMA Data Format
646
Diagram of DAC Function
647
DMA Support
648
Cosine Waveform (CW) Generator
648
Register Summary
649
ULP Coprocessor Diagram
665
Instruction Set
666
The ULP Coprocessor Instruction Format
666
ALU Operations Among Registers
667
Instruction Type - ALU for Operations Among Registers
667
ALU Operations with Immediate Value
668
Instruction Type - ALU for Operations with Immediate Value
668
Instruction Type - ALU for Operations with Stage Count Register
668
ALU Operations with Stage Count Register
669
Instruction Type - ST
669
Instruction Type - LD
669
Instruction Type - JUMP
670
Instruction Type - JUMPR
670
Instruction Type - JUMP
671
Instruction Type - HALT
671
Instruction Type - WAKE
672
Instruction Type - SLEEP
672
Instruction Type - WAIT
672
Instruction Type - ADC
672
Input Signals Measured Using the ADC Instruction
673
Instruction Type - I²C
673
Control of ULP Program Execution
675
Sample of a ULP Operation Sequence
676
I²C Read Operation
678
I²C Write Operation
678
Register
679
ESP32 Power Control
690
Digital Core Voltage Regulator
691
Low-Power Voltage Regulator
692
RTC Module
693
Flash Voltage Regulator
693
Brownout Detector
693
RTC Structure
694
RTC Low-Power Clocks
695
RTC Power Domains
696
RTC States
696
Power Modes
698
Wake-Up Source
700
ESP32 Boot Flow
702
System and
704
Memory. the
704
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Espressif ESP32 At Instruction Set (58 pages)
Brand:
Espressif
| Category:
Microcontrollers
| Size: 4 MB
Table of Contents
Table of Contents
3
Overview
6
User-Defined at Commands
6
Downloading at Firmware into Flash
6
Command Description
8
3 Basic at Commands
9
Overview
9
Commands
9
AT-Tests at Startup
9
AT+RST-Restarts the Module
9
AT+GMR-Checks Version Information
10
AT+GSLP-Enters Deep-Sleep Mode
10
ATE-AT Commands Echoing
10
AT+RESTORE-Restores the Factory Default Settings
10
AT+UART-UART Configuration
11
AT+UART_CUR-Current UART Configuration, Not Saved in Flash
12
AT+UART_DEF-Default UART Configuration, Saved in Flash
13
AT+SLEEP-Sets the Sleep Mode
14
AT+SYSRAM-Checks the Remaining Space of RAM
14
4 Wi-Fi at Commands
15
Overview
15
Commands
16
AT+CWMODE-Sets the Wi-Fi Mode (Station/Softap/Station+Softap)
16
AT+CWJAP-Connects to an AP
17
AT+CWLAPOPT-Sets the Configuration for the Command AT+CWLAP
18
AT+CWLAP-Lists the Available Aps
19
AT+CWQAP-Disconnects from the AP
19
AT+CWSAP-Configuration of the ESP32 Softap
20
AT+CWLIF-IP of Stations to Which the ESP32 Softap Is Connected
21
AT+CWDHCP-Enables/Disables DHCP
21
AT+CWDHCPS-Sets the IP Address Allocated by ESP32 Softap DHCP (the Configuration Is Saved in Flash.)
22
AT+CWAUTOCONN-Auto-Connects to the AP or Not
22
AT+CIPSTAMAC-Sets the MAC Address of the ESP32 Station
23
AT+CIPAPMAC-Sets the MAC Address of the ESP32 Softap
23
AT+CIPSTA-Sets the IP Address of the ESP32 Station
24
AT+CIPAP-Sets the IP Address of the ESP32 Softap
24
AT+CWSTARTSMART-Starts Smartconfig
25
AT+CWSTOPSMART-Stops Smartconfig
25
AT+WPS-Enables the WPS Function
26
5 TCP/IP-Related at Commands
27
Overview
27
Commands
28
AT+CIPSTATUS-Gets the Connection Status
28
AT+CIPDOMAIN-DNS Function
28
AT+CIPSTART-Establishes TCP Connection, UDP Transmission or SSL Connection
29
AT+CIPSEND-Sends Data
31
AT+CIPSENDEX-Sends Data
32
AT+CIPCLOSE-Closes TCP/UDP/SSL Connection
32
AT+CIFSR-Gets the Local IP Address
33
AT+CIPMUX-Enables/Disables Multiple Connections
33
AT+CIPSERVER-Deletes/Creates TCP Server
34
AT+CIPMODE-Configures the Transmission Mode
34
AT+SAVETRANSLINK-Saves the Transparent Transmission Link in Flash
35
AT+CIPSTO-Sets the TCP Server Timeout
36
AT+CIPSNTPCFG-Sets the Time Zone and the SNTP Server
36
AT+CIPSNTPTIME-Queries the SNTP Time
37
AT+CIUPDATE-Updates the Software through Wi-Fi
37
AT+CIPDINFO-Shows the Remote IP and Port with "+IPD
37
IPD-Receives Network Data
38
AT Commands with Configuration Saved in the NVS Area
39
7 AT Commands Examples
40
ESP32 as a TCP Client in Single Connection
40
UDP Transmission
41
UDP (with Fixed Remote IP and Port)
42
UDP (with Changeable Remote IP and Port)
43
Transparent Transmission
44
ESP32 as a TCP Client in UART-Wi-Fi Passthrough (Single Connection Mode)
44
UDP Transmission (UART-Wi-Fi Passthroughtransmission)
47
ESP32 as a TCP Server in Multiple Connections
50
OTA Update
52
9 Q & a
57
Espressif ESP32 User Manual (20 pages)
Brand:
Espressif
| Category:
Motherboard
| Size: 0 MB
Table of Contents
Table of Contents
3
Introduction
3
Esp32
3
Requirements
3
Hardware
3
Software
5
Getting Started
7
Getting Started to Use SDK
7
Process Overview
7
Building Toolchain
7
Building Firmware
10
Uploading Firmware
11
Running Application
14
SSC Command Reference
14
Sta
15
Mac
16
Dhcp
17
Reboot
18
Ram
18
Appendix - Notices
19
Federal Communications Commission (FCC) Declaration of Conformity
19
EC Declaration of Conformity
19
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Espressif ESP32 Manual (22 pages)
RF Performance Test Demonstration
Brand:
Espressif
| Category:
Microcontrollers
| Size: 6 MB
Table of Contents
Table of Contents
3
Demonstration Setup
4
Environment Setup
5
Environment Preparation
5
Hardware Preparation
5
Software Preparation
6
Hardware Connection
6
Software Installation
7
ESP-Launcher
8
Introduction to the Esprftesttool
9
RF Performance Test
11
RF Certification Test
17
Appendix - Install a UART Driver on ESP-Launcher
18
Appendix - ESP32 & ESP8266 RF Test Target Values
19
Espressif ESP32 User Manual (16 pages)
Bluetooth Networking
Brand:
Espressif
| Category:
Industrial Electrical
| Size: 3 MB
Table of Contents
Table of Contents
3
1 Introduction
4
Overview
4
Espblufi
4
2 Apis for Networking Development
6
Blufi Protocol
6
Apis on ESP32 End
6
Apis on the Espblufi APK End
7
3 ESP32 Bluetooth Networking Examples
8
Hardware and Software Preparation
8
Setting ESP32 to Station Mode
8
Setting ESP32 as a Softap
12
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