Espressif ESP32 Technical Reference Manual page 388

13 UART Controller (UART)
31
0 0 0 0 0 0 0
UHCI_DMA_OUT_DSCR_BF0_REG The address of the last outlink descriptor y-1. (RO)
31
0 0 0 0 0 0 0
UHCI_DMA_OUT_DSCR_BF1_REG The address of the second-to-last outlink descriptor y-2. (RO)
31
0 0 0 0 0 0 0
UHCI_RX_13_ESC_EN Set this bit to enable replacing flow control char 0x13, when DMA sends data.
(R/W)
UHCI_RX_11_ESC_EN Set this bit to enable replacing flow control char 0x11, when DMA sends data.
(R/W)
UHCI_RX_DB_ESC_EN Set this bit to enable replacing 0xdb char, when DMA sends data. (R/W)
UHCI_RX_C0_ESC_EN Set this bit to enable replacing 0xc0 char, when DMA sends data. (R/W)
UHCI_TX_13_ESC_EN Set this bit to enable decoding flow control char 0x13, when DMA receives
data. (R/W)
UHCI_TX_11_ESC_EN Set this bit to enable decoding flow control char 0x11, when DMA receives
data. (R/W)
UHCI_TX_DB_ESC_EN Set this bit to enable decoding 0xdb char, when DMA receives data. (R/W)
UHCI_TX_C0_ESC_EN Set this bit to enable decoding 0xc0 char, when DMA receives data. (R/W)
Espressif Systems
Register 13.48. UHCI_DMA_OUT_DSCR_BF0_REG (0x5C)
0 0 0 0 0 0 0 0
Register 13.49. UHCI_DMA_OUT_DSCR_BF1_REG (0x60)
0 0 0 0 0 0 0 0
Register 13.50. UHCI_ESCAPE_CONF_REG (0x64)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
388
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
0 0 0 1 1 0 0 1
ESP32 TRM (Version 5.2)
0
0
Reset
0
0 Reset
0
1
Reset