Espressif ESP32 Technical Reference Manual page 376

13 UART Controller (UART)
31 30 28 27 25
0 0x0 0x0
UART_TX_MEM_EMPTY_THRHD Refer to the description of TXFIFO_EMPTY_THRHD. (R/W)
UART_RX_MEM_FULL_THRHD Refer to the description of RXFIFO_FULL_THRHD. (R/W)
UART_XOFF_THRESHOLD_H2 Refer to the description of UART_XOFF_THRESHOLD. (R/W)
UART_XON_THRESHOLD_H2 Refer to the description of UART_XON_THRESHOLD. (R/W)
UART_RX_TOUT_THRHD_H3 Refer to the description of RX_TOUT_THRHD. (R/W)
UART_RX_FLOW_THRHD_H3 Refer to the description of RX_FLOW_THRHD. (R/W)
UART_TX_SIZE This register is used to configure the amount of memory allocated to the transmit-
FIFO. The default number is 128 bytes. (R/W)
UART_RX_SIZE This register is used to configure the amount of memory allocated to the receive-
FIFO. The default number is 128 bytes. (R/W)
UART_MEM_PD Set this bit to power down the memory. When the reg_mem_pd register is set to
1 for all UART controllers, Memory will enter the low-power mode. (R/W)
31
0
UART_MEM_TX_WR_ADDR Represents the offset address to write TX FIFO. (RO)
UART_MEM_TX_RD_ADDR Represents the offset address to read TX FIFO. (RO)
Espressif Systems
Register 13.23. UART_MEM_CONF_REG (0x58)
24 23 22 21 20 18 17
0x0 0x0 0x0
Register 13.24. UART_MEM_TX_STATUS_REG (0x5c)
24 23
0
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15 14 11 10
0x0 0 0 0 0 0x01
13 12
376
7 6 3 2 1 0
0x01 0 0 0
2 1 0
0 0
ESP32 TRM (Version 5.2)
Reset
Reset