Espressif ESP32 Technical Reference Manual page 343

12 I2S Controller (I2S)
31
0 0 0 0 0 0 0
I2S_INTER_VALID_EN Set this bit to enable camera's internal validation. (R/W)
I2S_EXT_ADC_START_EN Set this bit to enable the start of external ADC . (R/W)
I2S_LCD_EN Set this bit to enable LCD mode. (R/W)
I2S_LCD_TX_SDX2_EN Set this bit to duplicate data pairs (Data Frame, Form 2) in LCD mode. (R/W)
I2S_LCD_TX_WRX2_EN One datum will be written twice in LCD mode. (R/W)
I2S_CAMERA_EN Set this bit to enable camera mode. (R/W)
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2S_CLKA_ENA Set this bit to enable APLL_CLK. Default is PLL_F160M_CLK. (R/W)
I2S_CLKM_DIV_A Fractional clock divider's denominator value. (R/W)
I2S_CLKM_DIV_B Fractional clock divider's numerator value. (R/W)
I2S_CLKM_DIV_NUM I2S clock divider's integral value. (R/W)
Espressif Systems
Register 12.30. I2S_CONF2_REG (0x00a8)
0 0 0 0 0 0 0 0
Register 12.31. I2S_CLKM_CONF_REG (0x00ac)
22 21 20 19
0 0 0x00
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0 0 0 0 0 0 0 0
14 13
0x00
343
8 7 6 5 4 3 2 1
0 0 0 1 0 0 0 0
8 7
4
ESP32 TRM (Version 5.2)
0
0
Reset
0
Reset