Espressif ESP32 Technical Reference Manual page 567

21 Two-wire Automotive Interface (TWAI)
The Error Warning Interrupt is triggered whenever the value of the
bit) changes.
To return to the Error Active state, the TWAI controller must undergo Bus-Off recovery. Bus-Off recovery requires
the TWAI controller to observe 128 occurrences of 11 consecutive Recessive bits on the bus. To initiate Bus-
Off recovery (after entering the Bus-Off state), the TWAI controller should enter Operation Mode by setting the
TWAI_RESET_MODE bit to 0. The TEC tracks the progress of Bus-Off recovery by decrementing the TEC each
time the TWAI controller observes 11 consecutive Recessive bits. When Bus-Off recovery has completed (i.e.,
TEC has decremented from 127 to 0), the
the Error Warning Interrupt.
21.5.8 Error Code Capture
The Error Code Capture (ECC) feature allows the TWAI controller to record the error type and bit position of
a TWAI bus error in the form of an error code. Upon detecting a TWAI bus error, the Bus Error Interrupt is
triggered and the error code is recorded in the TWAI_ERR_CODE_CAP_REG. Subsequent bus errors will trigger
the Bus Error Interrupt, but their error codes will not be recorded until the current error code is read from the
TWAI_ERR_CODE_CAP_REG.
The following Table 21-16
Table 21-16. Bit Information of TWAI_ERR_CODE_CAP_REG; TWAI Address 0x30
Bit 31-8 Bit 7
1
Reserved ERRC.1
Notes:
• ERRC: The Error Code (ERRC) indicates the type of bus error: 00 for bit error, 01 for form error, 10 for stuff
error, 11 for other type of error.
• DIR: The Direction (DIR) indicates whether the TWAI controller was transmitting or receiving when the bus
error: 0 for Transmitter, 1 for Receiver.
• SEG: The Error Segment (SEG) indicates which segment of the TWAI message (i.e., bit position) the bus
error occurred at.
The following Table 21-17
Bit SEG.4 Bit SEG.3
0
0
0
0
0
0
0
0
0
Espressif Systems
TWAI_BUS_OFF_ST
shows the fields of the TWAI_ERR_CODE_CAP_REG:
Bit 6 Bit 5
1 2
ERRC.0 DIR
shows how to interpret the SEG.0 to SEG.4 bits.
Table 21-17. Bit Information of Bits SEG.4 - SEG.0
Bit SEG.2
0 0
0 0
0 1
0 1
0 1
0 1
1 1
1 1
1 1
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TWAI_BUS_OFF_ST
bit will automatically be reset to 0, thus triggering
Bit 4 Bit 3 Bit 2
3 3
SEG.4 SEG.3 SEG.2
Bit SEG.1 Bit SEG.0
1 1
1 0
1 0
0 0
0 1
1 1
1 1
1 0
0 0
567
bit (or the TWAI_ERR_ST
Bit 1 Bit 0
3 3 3
SEG.1 SEG.0
Description
start of frame
ID.28 to ID.21
ID.20 to ID.18
1
bit SRTR
2
bit IDE
ID.17 to ID.13
ID.12 to ID.5
ID.4 to ID.0
bit RTR
ESP32 TRM (Version 5.2)