Espressif ESP32 Technical Reference Manual page 171

8 SDIO Slave Controller
31 27 26
0x00 0 0
SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave sending descriptor error
(RO)
SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave receiving descriptor error.
(RO)
SLC0INT_SLC0_RX_EOF_INT_RAW The interrupt mark bit for Slave sending operation finished. (RO)
SLC0INT_SLC0_RX_DONE_INT_RAW The raw interrupt bit to mark single buffer as sent by Slave.
(RO)
SLC0INT_SLC0_TX_SUC_EOF_INT_RAW The raw interrupt bit to mark Slave receiving operation as
finished. (RO)
SLC0INT_SLC0_TX_DONE_INT_RAW The raw interrupt bit to mark a single buffer as finished during
Slave receiving operation. (RO)
SLC0INT_SLC0_TX_OVF_INT_RAW The raw interrupt bit to mark Slave receiving buffer overflow.
(RO)
SLC0INT_SLC0_RX_UDF_INT_RAW The raw interrupt bit for Slave sending buffer underflow. (RO)
SLC0INT_SLC0_TX_START_INT_RAW The raw interrupt bit for registering Slave receiving initialization
interrupt. (RO)
SLC0INT_SLC0_RX_START_INT_RAW The raw interrupt bit to mark Slave sending initialization inter-
rupt. (RO)
SLC0INT_SLC_FRHOST_BIT7_INT_RAW The interrupt mark bit 7 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT6_INT_RAW The interrupt mark bit 6 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT5_INT_RAW The interrupt mark bit 5 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT4_INT_RAW The interrupt mark bit 4 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT3_INT_RAW The interrupt mark bit 3 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT2_INT_RAW The interrupt mark bit 2 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT1_INT_RAW The interrupt mark bit 1 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT0_INT_RAW The interrupt mark bit 0 for Host to interrupt Slave. (RO)
Espressif Systems
Register 8.2. SLC0INT_RAW_REG (0x4)
21 20 19 18 17 16
0 0 0 0 0 0 0 0 0
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15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0 0
171
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 Reset
ESP32 TRM (Version 5.2)