27 Memory Management and Protection Units (MMU, MPU)
Table 27-15. Virtual Address for External SRAM ( Normal Mode )
Virtual address
L
V Addr
RAM
Virtual address
R
V Addr
RAM
In Low-High mode, both the PRO_CPU and the APP_CPU use the same mapping entries. In this mode
is used for the lower 2 MB of the virtual address space, while
also means that the upper 64 MMU entries for
are unused. Table
27-16
Table 27-16. Virtual Address for External SRAM ( Low-High Mode )
Virtual address
L
V Addr
RAM
R
V Addr
RAM
In Even-Odd memory, the VRAM is split into 32-byte chunks. The even chunks are resolved through the MMU
L
entries for
, the odd chunks through the entries for
V Addr
RAM
L
R
and
V Addr
V Addr
RAM
of physical memory. Table
Table 27-17. Virtual Address for External SRAM (Even-Odd Mode)
Virtual address
L
V Addr
RAM
R
V Addr
RAM
L
V Addr
RAM
R
V Addr
RAM
L
V Addr
RAM
R
V Addr
RAM
The bit configuration of the External RAM MMU entries is the same as for the flash memory: the entries are
32-bit registers, with the lower nine bits being used. Bits 0~7 contain the physical page the entry should map
its associate virtual page address to, while bit 8 is cleared when the entry is valid and set when it is not. Table
27-18
details the first MMU entry number for
Espressif Systems
Size
Low
4 MB
0x3F80_0000
Size
Low
4 MB
0x3F80_0000
L
details these address ranges.
Size
Low
2 MB
0x3F80_0000
2 MB
0x3FA0_0000
are set to the same values, so that the virtual pages map to a contiguous region
RAM
27-17
details this mode.
Size
Low
32 Bytes
0x3F80_0000
32 Bytes
0x3F80_0020
32 Bytes
0x3F80_0040
32 Bytes
0x3F80_0060
32 Bytes
0x3FBF_FFC0
32 Bytes
0x3FBF_FFE0
L
V Addr
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PRO_CPU address
APP_CPU address
R
V Addr
RAM
, as well as the lower 64 entries for
V Addr
RAM
PRO_CPU/APP_CPU address
R
V Addr
PRO_CPU/APP_CPU address
...
R
and
V Addr
RAM
RAM
622
High
0x3FBF_FFFF
High
0x3FBF_FFFF
is used for the upper 2 MB. This
R
High
0x3F9F_FFFF
0x3FBF_FFFF
. Generally, the MMU entries for
RAM
High
0x3F80_001F
0x3F80_003F
0x3F80_005F
0x3F80_007F
0x3FBF_FFDF
0x3FBF_FFFF
for all PIDs.
ESP32 TRM (Version 5.2)
L
V Addr
RAM
,
V Addr
RAM
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