Espressif ESP32 Technical Reference Manual page 224

9 SD/MMC Host Controller
31
0 0 0 0 0 0 0
IDINTEN_AI Abnormal Interrupt Summary Enable. (R/W)
When set, an abnormal interrupt is enabled. This bit enables the following bits:
IDINTEN[2]: Fatal Bus Error Interrupt;
IDINTEN[4]: DU Interrupt.
IDINTEN_NI Normal Interrupt Summary Enable. (R/W)
When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit
enables the following bits:
IDINTEN[0]: Transmit Interrupt;
IDINTEN[1]: Receive Interrupt.
IDINTEN_CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt sum-
mary. (R/W)
IDINTEN_DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
Enable, the DU interrupt is enabled. (R/W)
IDINTEN_FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. (R/W)
IDINTEN_RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
Interrupt is enabled. When reset, Receive Interrupt is disabled. (R/W)
IDINTEN_TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
Interrupt is enabled. When reset, Transmit Interrupt is disabled. (R/W)
31
DSCADDR_REG Host Descriptor Address Pointer, updated by IDMAC during operation and cleared
on reset. This register points to the start address of the current descriptor read by the IDMAC.
(RO)
Espressif Systems
Register 9.31. IDINTEN_REG (0x0090)
0 0 0 0 0 0 0 0
Register 9.32. DSCADDR_REG (0x0094)
0x000000000
Submit Documentation Feedback
10 9
0 0 0 0 0 0 0 0
224
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
Reset