Espressif ESP32 Technical Reference Manual page 128

7 SPI Controller (SPI)
7.2 SPI Features
General Purpose SPI (GP-SPI)
• Programmable data transfer length, in multiples of 1 byte
• Four-line full-duplex/half-duplex communication and three-line half-duplex communication support
• Master mode and slave mode
• Programmable CPOL and CPHA
• Programmable clock
Parallel QSPI
• Communication format support for specific slave devices such as flash
• Programmable communication format
• Six variations of flash-read operations available
• Automatic shift between flash and SRAM access
• Automatic wait states for flash access
SPI DMA Support
• Support for sending and receiving data using linked lists
SPI Interrupt Hardware
• SPI interrupts
• SPI DMA interrupts
7.3 GP-SPI
The SPI master mode supports four-line full-duplex/half-duplex communication and three-line half-duplex com-
munication. Figure 7-2 outlines the connections needed for four-line full-duplex/half-duplex communications.
Figure 7-2. SPI Master and Slave Full-duplex/Half-duplex Communication
The SPI1~SPI3 controllers can communicate with other slaves as a standard SPI master. SPI2 and SPI3 can be
configured as either a master or a slave. Every SPI master can be connected to three slaves at most by default.
When not using DMA, the maximum length of data received/sent in one burst is 64 bytes. The data length is in
multiples of one byte.
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