Espressif ESP32 Technical Reference Manual page 141

7 SPI Controller (SPI)
31 28 27 26 25
0x00 0x0
SPI_CS_DELAY_NUM Reserved.
SPI_CS_DELAY_MODE Reserved.
SPI_MOSI_DELAY_NUM It is used to configure the number of system clock cycles by which the
MOSI signals are delayed. (R/W)
SPI_MOSI_DELAY_MODE This register field determines the way the MOSI signals are delayed by
SPI clock. (R/W)
After being delayed by SPI_MOSI_DELAY_NUM system clocks, the MOSI signals will then be
delayed by the configuration of SPI_MOSI_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MOSI signals are delayed one cycle.
SPI_MISO_DELAY_NUM It is used to configure the number of system clock cycles by which the
MISO signals are delayed. (R/W)
SPI_MISO_DELAY_MODE This register field determines the way MISO signals are delayed by SPI
clock. (R/W)
After being delayed by SPI_MISO_DELAY_NUM system clock, the MISO signals will then be de-
layed by the configuration of SPI_MISO_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MISO signals are delayed by one cycle.
SPI_HOLD_TIME The number of SPI clock cycles by which CS pin signals are delayed. It is only
valid when SPI_CS_HOLD is set to 1. (R/W)
SPI_SETUP_TIME It is to configure the time between the CS signal active edge and the first SPI
clock edge. It is only valid in half-duplex mode or QSPI mode and when SPI_CS_SETUP is set
to 1. (R/W)
Espressif Systems
Register 7.6. SPI_CTRL2_REG (0x14)
23 22 21 20 18 17
0x0 0x0 0x0 0x0
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16 15 12 11
0x00 0x00
141
8 7 4 3
0x01 0x01
ESP32 TRM (Version 5.2)
0
Reset