Espressif ESP32 Technical Reference Manual page 76

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
Register 4.32. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-19, 21-23, 25-27, 32-33) (0x530+0x4*n)
31
0 0 0 0 0 0 0
GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable
signal. (R/W)
GPIO_FUNCn_OEN_SEL 1:
GPIO_ENABLE_REG; 0: use output enable signal from peripheral. (R/W)
GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W)
GPIO_FUNCn_OUT_SEL Selection control for GPIO output n.
connects peripheral output
GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG as the output
value and output enable. (R/W)
4.13.2 IO MUX Registers
The addresses in parenthesis besides register names are the register addresses relative to the IO MUX base
addresses provided in Table
register addresses are listed in Section
Espressif Systems
0 0 0 0 0 0 0 0
Force the output enable signal to be sourced from bit
s to GPIO output n.
1-6 Peripheral Address Mapping in Chapter
4.12.2 IO MUX Register
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12 11 10 9
0 0 0 0 0 x x x
A value of 256 selects bit
1 System and
Summary.
76
8
x x x x x x x x
A value of s (0<=s<256)
Memory. The absolute
ESP32 TRM (Version 5.2)
0
x
Reset
n of
n of