Espressif ESP32 Technical Reference Manual page 138

7 SPI Controller (SPI)
7.8 Registers
The addresses in parenthesis besides register names are the register addresses relative to the SPI0/SPI1/SPI2/SPI3
base addresses provided in Table
solute register addresses are listed in Section
31
0 0 0 0 0 0 0
SPI_USR An SPI operation will be triggered when this bit is set. The bit will be cleared once the
operation is done. (R/W)
31
SPI_ADDR_REG It stores the transmitting address when master is in half-duplex mode or QSPI mode.
If the address length is bigger than 32 bits, this register stores the higher 32 bits of address value,
SPI_SLV_WR_STATUS_REG
smaller than 33 bits, this register stores all the address value. The register is in valid only when
SPI_USR_ADDR
Espressif Systems
1-6 Peripheral Address Mapping in Chapter
7.7 Register
Register 7.1. SPI_CMD_REG (0x0)
19 18 17
0 0 0 0 0 0 0 0
Register 7.2. SPI_ADDR_REG (0x4)
0x000000000
stores the rest lower part of address value. If the address length is
bit is set to 1. (R/W)
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Summary.
0 0 0 0 0 0 0 0
138
1 System and Memory. The ab-
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
Reset