Espressif ESP32 Technical Reference Manual page 324

12 I2S Controller (I2S)
The clock configuration of the LCD master transmitting mode is identical to I2S' clock configuration. In the LCD
mode, the frequency of WS is half of f
In the ADC/DAC mode, use PLL_F160M_CLK as the clock source.
12.5.1 LCD Master Transmitting Mode
As is shown in Figure 12-13, the WR signal of LCD connects to the WS signal of I2S. The LCD data bus width is
24 bits.
The I2S_LCD_EN bit of register I2S_CONF2_REG needs to be set and the I2S_TX_SLAVE_MOD bit of register
I2S_CONF_REG needs to be cleared, in order to configure I2S to the LCD master transmitting mode. Mean-
while, data should be sent under the correct mode, according to the I2S_TX_CHAN_MOD[2:0] bit of regis-
ter I2S_CONF_CHAN_REG and the I2S_TX_FIFO_MOD[2:0] bit of register I2S_FIFO_CONF_REG. The WS signal
needs to be inverted when it is routed through the GPIO Matrix. For details, please refer to the chapter about
IO_MUX and the GPIO Matrix. The I2S_LCD_TX_SDX2_EN bit and the I2S_LCD_TX_WRX2_EN bit of register
I2S_CONF2_REG should be set to the LCD master transmitting mode, so that both the data bus and WR signal
work in the appropriate mode.
As is shown in Figure 12-14
bit should be set to 0 in the data frame, form 1. Both I2S_LCD_TX_SDX2_EN bit and I2S_LCD_TX_WRX2_EN bit
are set to 1 in the data frame, form 2.
12.5.2 Camera Slave Receiving Mode
ESP32 I2S supports a camera slave mode for high-speed data transfer from external camera modules. As
shown in Figure 12-16, in this mode, I2S is set to slave receiving mode. Besides the 16-channel data signal bus
Espressif Systems
.
BCK
Figure 12-13. LCD Master Transmitting Mode
Figure 12-14. LCD Master Transmitting Data Frame, Form 1
Figure 12-15. LCD Master Transmitting Data Frame, Form 2
and Figure 12-15, the I2S_LCD_TX_WRX2_EN bit should be set to 1 and the I2S_LCD_TX_SDX2_EN
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324 ESP32 TRM (Version 5.2)