Espressif ESP32 Technical Reference Manual page 20

List of Figures
10-3 MII Interface
10-4 MII Clock
10-5 RMII Interface
10-6 RMII Clock
10-7 RMII Timing - Receiving Data
10-8 RMII Timing – Transmitting Data
10-9 Transmit Descriptor
10-10 Receive Descriptor
11-1 I2C Master Architecture
11-2 I2C Slave Architecture
11-3 I2C Sequence Chart
11-4 Structure of The I2C Command Register
11-5 I2C Master Writes to Slave with 7-bit Address
11-6 I2C Master Writes to Slave with 10-bit Address
11-7 I2C Master Writes to addrM in RAM of Slave with 7-bit Address
11-8 Master Writes to Slave with 7-bit Address in Three Segments
11-9 Master Reads from Slave with 7-bit Address
11-10 Master Reads from Slave with 10-bit Address
11-11 Master Reads N Bytes of Data from addrM in Slave with 7-bit Address
11-12 Master Reads from Slave with 7-bit Address in Three Segments
12-1 I2S System Block Diagram
12-2 I2S Clock
12-3 Philips Standard
12-4 MSB Alignment Standard
12-5 PCM Standard
12-6 Tx FIFO Data Mode
12-7 The First Stage of Receiving Data
12-8 Modes of Writing Received Data into FIFO
12-9 PDM Transmitting Module
12-10 PDM Sends Signal
12-11 PDM Receives Signal
12-12 PDM Receive Module
12-13 LCD Master Transmitting Mode
12-14 LCD Master Transmitting Data Frame, Form 1
12-15 LCD Master Transmitting Data Frame, Form 2
12-16 Camera Slave Receiving Mode
12-17 ADC Interface of I2S0
12-18 DAC Interface of I2S
12-19 Data Input by I2S DAC Interface
13-1 UART Basic Structure
13-2 UART Shared RAM
13-3 UART Data Frame Structure
13-4 AT_CMD Character Format
13-5 Hardware Flow Control
14-1 LED_PWM Architecture
14-2 LED_PWM High-speed Channel Diagram
Espressif Systems 20
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ESP32 TRM (Version 5.2)