Espressif ESP32 Technical Reference Manual page 488

16 Motor Control PWM (PWM)
31
0 0 0 0 0 0 0
PWM_EVENT_F2 Set and reset by hardware. If set, event_f2 is on-going. (RO)
PWM_EVENT_F1 Set and reset by hardware. If set, event_f1 is on-going. (RO)
PWM_EVENT_F0 Set and reset by hardware. If set, event_f0 is on-going. (RO)
PWM_F2_POLE Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
level high. (R/W)
PWM_F1_POLE Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
level high. (R/W)
PWM_F0_POLE Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
level high. (R/W)
PWM_F2_EN Set to enable the generation of event_f2. (R/W)
PWM_F1_EN Set to enable the generation of event_f1. (R/W)
PWM_F0_EN Set to enable the generation of event_f0. (R/W)
31
0 0 0 0 0 0 0
PWM_CAP_SYNC_SW Set this bit to force a capture timer sync; the capture timer is loaded with
the value in the phase register. (WO)
PWM_CAP_SYNCI_SEL Capture module sync input selection. 0: none, 1: timer0 sync_out, 2:
timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
SYNC2 from GPIO matrix. (R/W)
PWM_CAP_SYNCI_EN When set, the capture timer sync is enabled. (R/W)
PWM_CAP_TIMER_EN When set, the capture timer incrementing under APB_clk is enabled. (R/W)
Espressif Systems
Register 16.58. PWM_FAULT_DETECT_REG (0x00e4)
0 0 0 0 0 0 0 0
Register 16.59. PWM_CAP_TIMER_CFG_REG (0x00e8)
0 0 0 0 0 0 0 0
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9
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
488
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
6 5 4 2 1
0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0 Reset
0
0 Reset