Espressif ESP32 Technical Reference Manual page 558

21 Two-wire Automotive Interface (TWAI)
21.5.2 Bit Timing
The operating bit rate of the TWAI controller must be configured whilst the TWAI controller is in Reset Mode.
The bit rate configuration is located in
registers contain the following fields:
The following Table 21-6
Table 21-6. Bit Information of TWAI_CLOCK_DIVIDER_REG; TWAI Address 0x18
Bit 31-8 Bit 7
Reserved SJW.1
Notes:
• SJW: Synchronization Jump Width (SJW) is configured in SJW.0 and SJW.1 where SJW = (2 x SJW.1 + SJW.0
+ 1).
• BRP: The TWAI Time Quanta clock is derived from a prescaled version of the APB clock that is usually
80 MHz. The Baud Rate Prescaler (BRP) field is used to define the prescaler according to the equation
below, where t is the Time Quanta clock period and t
T q
t = 2 × t × (2
T q CLK
The following Table 21-7
Table 21-7. Bit Information of TWAI_BUS_TIMING_1_REG; TWAI Address 0x1c
Bit 31-8 Bit 7
Reserved SAM
Notes:
• PBS1: The number of Time Quanta in Phase Buffer Segment 1 is defined according to the following equa-
tion: (8 x PBS1.3 + 4 x PBS1.2 + 2 x PBS1.1 + PBS1.0 + 1).
• PBS2: The number of Time Quanta in Phase Buffer Segment 2 is defined according to the following
equation: (4 x PBS2.2 + 2 x PBS2.1 + PBS2.0 + 1).
• SAM: Enables triple sampling if set to 1. This is useful for low/medium speed buses where filtering spikes
on the bus line is beneficial.
21.5.3 Interrupt Management
The ESP32 TWAI controller provides seven interrupts, each represented by a single bit in the TWAI_INT_RAW_REG.
For a particular interrupt to be triggered (i.e., its bit in
enable bit in TWAI_INT ENA_REG
The TWAI controller provides the seven following interrupts:
• Receive Interrupt
• Transmit Interrupt
• Error Warning Interrupt
Espressif Systems
TWAI_BUS_TIMING_0_REG
illustrates the bit fields of TWAI_BUS_TIMING_0_REG.
Bit 6 Bit 5
SJW.0 BRP.5
5 4
× BRP.5 + 2 × BRP.4 + 2
illustrates the bit fields of TWAI_BUS_TIMING_1_REG.
Bit 6 Bit 5
PBS2.2 PBS2.1
must be set.
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and TWAI_BUS_TIMING_1_REG, and the two
Bit 4 Bit 3 Bit 2
BRP.4 BRP.3 BRP.2
is APB clock period :
CLK
3 2
× BRP.3 + 2 × BRP.2 + 2
Bit 4 Bit 3 Bit 2
PBS2.0 PBS1.3 PBS1.2
TWAI_INT_RAW_REG set to 1), the interrupt's corresponding
558
Bit 1 Bit 0
BRP.1 BRP.0
1 0
× BRP.1 + 2 × BRP.0 + 1)
Bit 1 Bit 0
PBS1.1 PBS1.0
ESP32 TRM (Version 5.2)