Espressif ESP32 Technical Reference Manual page 147

7 SPI Controller (SPI)
31 30 29 28 27 26
0 0 0 0 0 0 0
SPI_SYNC_RESET When set, it resets the latched values of the SPI clock line, CS line and data line.
(R/W)
SPI_SLAVE_MODE This bit is used to set the mode of the SPI device. (R/W)
1: slave mode;
0: master mode.
SPI_SLV_WR_RD_BUF_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read data commands are enabled. (R/W)
SPI_SLV_WR_RD_STA_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read status commands are enabled. (R/W)
SPI_SLV_CMD_DEFINE Reserved.
SPI_TRANS_CNT The counter for operations in both the master mode and the slave mode. (RO)
SPI_SLV_LAST_STATE In slave mode, this contains the state of the SPI state machine. (RO)
SPI_SLV_LAST_COMMAND Reserved.
SPI_CS_I_MODE Reserved.
SPI_TRANS_INTEN The interrupt enable bit for the
SPI_SLV_WR_STA_INTEN The interrupt enable bit for the
SPI_SLV_RD_STA_INTEN The interrupt enable bit for the
SPI_SLV_WR_BUF_INTEN The interrupt enable bit for the
SPI_SLV_RD_BUF_INTEN The interrupt enable bit for the
SPI_TRANS_DONE The raw interrupt status bit for the
hardware and cleared by software. (R/W)
SPI_SLV_WR_STA_DONE The raw interrupt status bit for the
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
SPI_SLV_RD_STA_DONE The raw interrupt status bit for the
by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
Continued on the next page...
Espressif Systems
Register 7.15. SPI_SLAVE_REG (0x38)
23 22 20 19 17
0 0 0 0 0 0 0 0
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16 12 11 10 9
0 0 0 0 0 0 0 0
SPI_TRANS_DONE_INT
SPI_SLV_WR_STA_INT
SPI_SLV_RD_STA_INT
SPI_SLV_WR_BUF_INT
SPI_SLV_RD_BUF_INT
SPI_TRANS_DONE_INT
SPI_SLV_WR_STA_INT
SPI_SLV_RD_STA_INT
147
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. It is set by
interrupt. It is
interrupt. It is set
ESP32 TRM (Version 5.2)
0
0
Reset