Espressif ESP32 Technical Reference Manual page 110

5 DPort Registers
31
0 0 0 0 0 0 0
DPORT_CACHE_MUX_MODE The mode of the two caches sharing the memory. (R/W)
31
0 0 0 0 0 0 0
DPORT_IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W)
31
0 0 0 0 0 0 0
DPORT_DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W)
31
DPORT_AHB_MPU_TABLE_0_REG MPU for DMA. (R/W)
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Register 5.14. DPORT_CACHE_MUX_MODE_REG (0x07C)
0 0 0 0 0 0 0 0
Register 5.15. DPORT_IMMU_PAGE_MODE_REG (0x080)
0 0 0 0 0 0 0 0
Register 5.16. DPORT_DMMU_PAGE_MODE_REG (0x084)
0 0 0 0 0 0 0 0
Register 5.17. DPORT_AHB_MPU_TABLE_0_REG (0x0B4)
0xFFFFFFFF
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0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
110
2 1
0 0 0 0 0 0 0 0
3 2 1
0 0 0 0 0 0 0 0
3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
0 Reset
0
0
Reset
0
Reset