Espressif ESP32 Technical Reference Manual page 36

Peripheral Interrupt
Configuration Register
Bit
DPORT_PRO_MAC_INTR_MAP_REG 0
DPORT_PRO_MAC_NMI_MAP_REG 1
DPORT_PRO_BB_INT_MAP_REG 2
DPORT_PRO_BT_MAC_INT_MAP_REG 3
DPORT_PRO_BT_BB_INT_MAP_REG 4
DPORT_PRO_BT_BB_NMI_MAP_REG 5
DPORT_PRO_RWBT_IRQ_MAP_REG 6
DPORT_PRO_RWBLE_IRQ_MAP_REG 7
DPORT_PRO_RWBT_NMI_MAP_REG 8
DPORT_PRO_RWBLE_NMI_MAP_REG 9
DPORT_PRO_SLC0_INTR_MAP_REG 10
DPORT_PRO_SLC1_INTR_MAP_REG 11
DPORT_PRO_UHCI0_INTR_MAP_REG 12
DPORT_PRO_UHCI1_INTR_MAP_REG 13
DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG 14
DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG 15
DPORT_PRO_INTR_STATUS_REG_0_REG
DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG 16
DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG 17
DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG 18
DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG 19
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG 20
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG 21
DPORT_PRO_GPIO_INTERRUPT_MAP_REG 22
DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG 23
DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24
DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25
DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26
DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27
DPORT_PRO_SPI_INTR_0_MAP_REG 28
DPORT_PRO_SPI_INTR_1_MAP_REG 29
DPORT_PRO_SPI_INTR_2_MAP_REG 30
DPORT_PRO_SPI_INTR_3_MAP_REG 31
DPORT_PRO_I2S0_INT_MAP_REG 0
DPORT_PRO_I2S1_INT_MAP_REG 1
DPORT_PRO_UART_INTR_MAP_REG 2
DPORT_PRO_UART1_INTR_MAP_REG 3
DPORT_PRO_UART2_INTR_MAP_REG 4
DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG 5
DPORT_PRO_EMAC_INT_MAP_REG 6
DPORT_PRO_PWM0_INTR_MAP_REG 7
DPORT_PRO_PWM1_INTR_MAP_REG 8
Reserved 9
Reserved 10
DPORT_PRO_INTR_STATUS_REG_1_REG
DPORT_PRO_LEDC_INT_MAP_REG 11
DPORT_PRO_EFUSE_INT_MAP_REG 12
DPORT_PRO_TWAI_INT_MAP_REG 13
DPORT_PRO_RTC_CORE_INTR_MAP_REG 14
DPORT_PRO_RMT_INTR_MAP_REG 15
DPORT_PRO_PCNT_INTR_MAP_REG 16
DPORT_PRO_I2C_EXT0_INTR_MAP_REG 17
DPORT_PRO_I2C_EXT1_INTR_MAP_REG 18
DPORT_PRO_RSA_INTR_MAP_REG 19
DPORT_PRO_SPI1_DMA_INT_MAP_REG 20
Table 2-1. PRO_CPU, APP_CPU Interrupt Configuration
PRO_CPU
Peripheral Interrupt Source
Status Register
No.
Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 GPIO_INTERRUPT_PRO
23 GPIO_INTERRUPT_PRO_NMI
24 CPU_INTR_FROM_CPU_0
25 CPU_INTR_FROM_CPU_1
26 CPU_INTR_FROM_CPU_2
27 CPU_INTR_FROM_CPU_3
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name No.
MAC_INTR 0
MAC_NMI 1
BB_INT 2
BT_MAC_INT 3
BT_BB_INT 4
BT_BB_NMI 5
RWBT_IRQ 6
RWBLE_IRQ 7
RWBT_NMI 8
RWBLE_NMI 9
SLC0_INTR 10
SLC1_INTR 11
UHCI0_INTR 12
UHCI1_INTR 13
TG_T0_LEVEL_INT 14
TG_T1_LEVEL_INT 15
DPORT_APP_INTR_STATUS_REG_0_REG
TG_WDT_LEVEL_INT 16
TG_LACT_LEVEL_INT 17
TG1_T0_LEVEL_INT 18
TG1_T1_LEVEL_INT 19
TG1_WDT_LEVEL_INT 20
TG1_LACT_LEVEL_INT 21
GPIO_INTERRUPT_APP 22
GPIO_INTERRUPT_APP_NMI 23
24
25
26
27
SPI_INTR_0 28
SPI_INTR_1 29
SPI_INTR_2 30
SPI_INTR_3 31
I2S0_INT 32
I2S1_INT 33
UART_INTR 34
UART1_INTR 35
UART2_INTR 36
SDIO_HOST_INTERRUPT 37
EMAC_INT 38
PWM0_INTR 39
PWM1_INTR 40
Reserved 41
Reserved 42
DPORT_APP_INTR_STATUS_REG_1_REG
LEDC_INT 43
EFUSE_INT 44
TWAI_INT 45
RTC_CORE_INTR 46
RMT_INTR 47
PCNT_INTR 48
I2C_EXT0_INTR 49
I2C_EXT1_INTR 50
RSA_INTR 51
SPI1_DMA_INT 52
APP_CPU
Peripheral Interrupt
Status Register
Configuration Register
Name Bit
0 DPORT_APP_MAC_INTR_MAP_REG
1 DPORT_APP_MAC_NMI_MAP_REG
2 DPORT_APP_BB_INT_MAP_REG
3 DPORT_APP_BT_MAC_INT_MAP_REG
4 DPORT_APP_BT_BB_INT_MAP_REG
5 DPORT_APP_BT_BB_NMI_MAP_REG
6 DPORT_APP_RWBT_IRQ_MAP_REG
7 DPORT_APP_RWBLE_IRQ_MAP_REG
8 DPORT_APP_RWBT_NMI_MAP_REG
9 DPORT_APP_RWBLE_NMI_MAP_REG
10 DPORT_APP_SLC0_INTR_MAP_REG
11 DPORT_APP_SLC1_INTR_MAP_REG
12 DPORT_APP_UHCI0_INTR_MAP_REG
13 DPORT_APP_UHCI1_INTR_MAP_REG
14 DPORT_APP_TG_T0_LEVEL_INT_MAP_REG
15 DPORT_APP_TG_T1_LEVEL_INT_MAP_REG
16 DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG
17 DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG
18 DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG
19 DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG
20 DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG
21 DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG
22 DPORT_APP_GPIO_INTERRUPT_MAP_REG
23 DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG
24 DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG
25 DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG
26 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG
27 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG
28 DPORT_APP_SPI_INTR_0_MAP_REG
29 DPORT_APP_SPI_INTR_1_MAP_REG
30 DPORT_APP_SPI_INTR_2_MAP_REG
31 DPORT_APP_SPI_INTR_3_MAP_REG
0 DPORT_APP_I2S0_INT_MAP_REG
1 DPORT_APP_I2S1_INT_MAP_REG
2 DPORT_APP_UART_INTR_MAP_REG
3 DPORT_APP_UART1_INTR_MAP_REG
4 DPORT_APP_UART2_INTR_MAP_REG
5 DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG
6 DPORT_APP_EMAC_INT_MAP_REG
7 DPORT_APP_PWM0_INTR_MAP_REG
8 DPORT_APP_PWM1_INTR_MAP_REG
9 Reserved
10 Reserved
11 DPORT_APP_LEDC_INT_MAP_REG
12 DPORT_APP_EFUSE_INT_MAP_REG
13 DPORT_APP_TWAI_INT_MAP_REG
14 DPORT_APP_RTC_CORE_INTR_MAP_REG
15 DPORT_APP_RMT_INTR_MAP_REG
16 DPORT_APP_PCNT_INTR_MAP_REG
17 DPORT_APP_I2C_EXT0_INTR_MAP_REG
18 DPORT_APP_I2C_EXT1_INTR_MAP_REG
19 DPORT_APP_RSA_INTR_MAP_REG
20 DPORT_APP_SPI1_DMA_INT_MAP_REG