Espressif ESP32 Technical Reference Manual page 332

12 I2S Controller (I2S)
31
0 0 0 0 0 0 0
I2S_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the
terrupt. (RO)
I2S_IN_DSCR_EMPTY_INT_ST The masked interrupt status bit for the
interrupt. (RO)
I2S_OUT_DSCR_ERR_INT_ST The masked interrupt status bit for the
terrupt. (RO)
I2S_IN_DSCR_ERR_INT_ST The masked interrupt status bit for the
rupt. (RO)
I2S_OUT_EOF_INT_ST The masked interrupt status bit for the
I2S_OUT_DONE_INT_ST The masked interrupt status bit for the
I2S_IN_SUC_EOF_INT_ST The masked interrupt status bit for the
(RO)
I2S_IN_DONE_INT_ST The masked interrupt status bit for the I2S_IN_DONE_INT interrupt. (RO)
I2S_TX_HUNG_INT_ST The masked interrupt status bit for the
I2S_RX_HUNG_INT_ST The masked interrupt status bit for the
I2S_TX_REMPTY_INT_ST The masked interrupt status bit for the
(RO)
I2S_TX_WFULL_INT_ST The masked interrupt status bit for the
I2S_RX_REMPTY_INT_ST The masked interrupt status bit for the
(RO)
I2S_RX_WFULL_INT_ST The masked interrupt status bit for the
I2S_TX_PUT_DATA_INT_ST The masked interrupt status bit for the
(RO)
I2S_RX_TAKE_DATA_INT_ST The masked interrupt status bit for the
rupt. (RO)
Espressif Systems
Register 12.5. I2S_INT_ST_REG (0x0010)
17
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
I2S_OUT_EOF_INT
I2S_OUT_DONE_INT
I2S_IN_SUC_EOF_INT
I2S_TX_HUNG_INT
I2S_RX_HUNG_INT
I2S_TX_REMPTY_INT
I2S_TX_WFULL_INT
I2S_RX_REMPTY_INT
I2S_RX_WFULL_INT
I2S_TX_PUT_DATA_INT
I2S_RX_TAKE_DATA_INT
332
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
I2S_OUT_TOTAL_EOF_INT
I2S_IN_DSCR_EMPTY_INT
I2S_OUT_DSCR_ERR_INT
I2S_IN_DSCR_ERR_INT
interrupt. (RO)
interrupt. (RO)
interrupt.
interrupt. (RO)
interrupt. (RO)
interrupt.
interrupt. (RO)
interrupt.
interrupt. (RO)
interrupt.
ESP32 TRM (Version 5.2)
0
0
Reset
in-
in-
inter-
inter-