Espressif ESP32 Technical Reference Manual page 112

5 DPort Registers
31 27 26 25
11111 0 0
Set the following bit to enable the clock of the corresponding module. Clear the bit to disable the
clock of the corresponding module.
DPORT_UART_MEM_CLK_EN Shared memory of UART0 ~ 2. To use any UART peripherals, enable
the clock for UART memory. (R/W)
DPORT_UART2_CLK_EN UART2 module. (R/W)
DPORT_SPI_DMA_CLK_EN SPI_DMA module. (R/W)
DPORT_I2S1_CLK_EN I2S1 module. (R/W)
DPORT_PWM1_CLK_EN PWM1 module. (R/W)
DPORT_TWAI_CLK_EN TWAI module. (R/W)
DPORT_I2C_EXT1_CLK_EN I2C1 module. (R/W)
DPORT_PWM0_CLK_EN PWM0 module. (R/W)
DPORT_SPI3_CLK_EN SPI3 module. (R/W)
DPORT_TIMERGROUP1_CLK_EN TIMG1 module. (R/W)
DPORT_EFUSE_CLK_EN eFuse module. (R/W)
DPORT_TIMERGROUP_CLK_EN TIMG0 module. (R/W)
DPORT_UHCI1_CLK_EN UDMA1 module. (R/W)
DPORT_LEDC_CLK_EN LEDC module. (R/W)
DPORT_PCNT_CLK_EN PCNT module. (R/W)
DPORT_RMT_CLK_EN RMT module. (R/W)
DPORT_UHCI0_CLK_EN UDMA0 module. (R/W)
DPORT_I2C_EXT0_CLK_EN I2C0 module. (R/W)
DPORT_SPI2_CLK_EN SPI2 module. (R/W)
Continued on the next page...
Espressif Systems
Register 5.19. DPORT_PERIP_CLK_EN_REG (0x0C0)
24 23 22 21 20 19 18 17
1 1 1 0 0 0 0 0
Submit Documentation Feedback
16 15 14 13 12 11 10 9
1 1 1 1 0 0 0 0
112
8 7 6 5 4 3 2 1
0 0 1 1 0 1 1 1
ESP32 TRM (Version 5.2)
0
1
Reset