Espressif ESP32 Technical Reference Manual page 134

7 SPI Controller (SPI)
ESP32 QSPI supports flash-read operation in one-line, two-line, and four-line modes. When working as a QSPI
master, the command phase, address phase, dummy phase and data phase can be configured as needed, as
flexible as in GP-SPI mode.
Note that GPI-SPI full-duplex mode does not support dummy phase.
7.6 GP-SPI Interrupt Hardware
ESP32 SPI generates two types of interrupts. One is the SPI interrupt and the other is the SPI DMA inter-
rupt.
ESP32 SPI reckons the completion of send- and/or receive-operations as the completion of one operation from
the controller and generates one interrupt. When ESP32 SPI is configured to slave mode, the slave will generate
read/write status registers and read/write buffer data interrupts according to different operations.
7.6.1 SPI Interrupts
The SPI_*_INTEN bits in the SPI_SLAVE_REG register can be set to enable SPI interrupts. When an SPI interrupt
happens, the interrupt flag in the corresponding SPI_*_DONE register will get set. This flag is writable, and an
interrupt can be cleared by setting the bit to zero.
• SPI_TRANS_DONE_INT: Triggered when an SPI operation is done.
• SPI_SLV_WR_STA_INT: Triggered when an SPI slave status write is done.
• SPI_SLV_RD_STA_INT: Triggered when an SPI slave status read is done.
• SPI_SLV_WR_BUF_INT: Triggered when an SPI slave buffer write is done.
• SPI_SLV_RD_BUD_INT: Triggered when an SPI slave buffer read is done.
7.6.2 DMA Interrupts
• SPI_OUT_TOTAL_EOF_INT: Triggered when all linked lists are sent.
• SPI_OUT_EOF_INT: Triggered when one linked list is sent.
• SPI_OUT_DONE_INT: Triggered when the last linked list item has zero length.
• SPI_IN_SUC_EOF_INT: Triggered when all linked lists are received.
• SPI_IN_ERR_EOF_INT: Triggered when there is an error receiving linked lists.
• SPI_IN_DONE_INT: Triggered when the last received linked list had a length of 0.
• SPI_INLINK_DSCR_ERROR_INT: Triggered when the received linked list is invalid.
Espressif Systems
Figure 7-6. Communication Format of Parallel QSPI
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