Espressif ESP32 Technical Reference Manual page 249

10 Ethernet Media Access Controller (MAC)
Bits Name
[6] IPv4 Packet Received
[5] IP Checksum Bypassed
[4] IP Payload Error
[3] IP Header Error
[2:0] IP Payload Type
10.9 Register Summary
Note that specific fields or bits of a given register may have different access attributes. Below is the list of all
attributes together with the abbreviations used in register descriptions.
• Read Only (RO)
• Write Only (WO)
• Read and Write (R/W)
• Read, Write, and Self Clear (R/W/SC)
• Read, Self Set, and Write Clear (R/SS/WC)
• Read, Write Set, and Self Clear (R/WS/SC)
• Read, Self Set, and Self Clear or Write Clear (R/SS/SC/WC)
• Read Only and Write Trigger (RO/WT)
• Read, Self Set, and Read Clear (R/SS/RC)
Espressif Systems
Description
When set, this bit indicates that the received packet is an IPv4
packet. This bit is updated only when Bit[10] (IPC) of Register
(MAC Configuration Register) is set.
When set, this bit indicates that the checksum offload engine is
bypassed.
When set, this bit indicates that the 16-bit IP payload checksum
(that is, the TCP, UDP, or ICMP checksum) that the core calculated
does not match the corresponding checksum field in the received
segment. It is also set when the TCP, UDP, or ICMP segment
length does not match the payload length value in the IP Header
field. This bit is valid when either Bit 7 or Bit 6 is set.
When set, this bit indicates that either the 16-bit IPv4 header
checksum calculated by the core does not match the received
checksum bytes, or the IP datagram version is not consistent with
the Ethernet Type value. This bit is valid when either Bit[7] or Bit[6]
is set.
These bits indicate the type of payload encapsulated in the IP
datagram processed by the Receive Checksum Offload Engine
(COE). The COE also sets these bits to 2'b00 if it does not process
the IP datagram's payload due to an IP header error or fragmented
IP.
• 3'b000: Unknown or did not process IP payload
• 3'b001: UDP
• 3'b010: TCP
• 3'b011: ICMP
• 3'b1xx: Reserved
This bit is valid when either Bit[7] or Bit[6] is set.
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ESP32 TRM (Version 5.2)