Espressif ESP32 Technical Reference Manual page 7

Contents
10.2.1.1
10.2.1.2
10.2.2 Receive Operation
10.2.2.1
10.2.2.2 Receive Frame Controller
10.2.2.3 Receive Flow Control
10.2.2.4 Reception of Multiple Frames
10.2.2.5 Error Handling
10.2.2.6 Receive Status Word
10.3 MAC Interrupt Controller
10.4 MAC Address Filtering
10.4.1 Unicast Destination Address Filtering
10.4.2 Multicast Destination Address Filtering
10.4.3 Broadcast Address Filtering
10.4.4 Unicast Source Address Filtering
10.4.5 Inverse Filtering Operation
10.4.6 Good Transmitted Frames and Received Frames
10.5 EMAC_MTL (MAC Transaction Layer)
10.6 PHY Interface
10.6.1 MII (Media Independent Interface)
10.6.1.1
10.6.1.2
10.6.2 RMII (Reduced Media-Independent Interface)
10.6.2.1
10.6.2.2 RMII Clock
10.6.3 Station Management Agent (SMA) Interface
10.6.4 RMII Timing
10.7 Ethernet DMA Features
10.8 Linked List Descriptors
10.8.1 Transmit Descriptors
10.8.2 Receive Descriptors
10.9 Register Summary
10.10 Registers
11 I2C Controller (I2C)
11.1 Overview
11.2 Features
11.3 Functional Description
11.3.1 Introduction
11.3.2 Architecture
11.3.3 I2C Bus Timing
11.3.4 I2C cmd Structure
11.3.5 I2C Master Writes to Slave
11.3.6 Master Reads from Slave
11.3.7 Interrupts
11.4 Register Summary
Espressif Systems
Transmit Flow Control
Retransmission During a Collision
Reception Protocol
Interface Signals Between MII and PHY
MII Clock
RMII Interface Signal Description
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ESP32 TRM (Version 5.2)