Espressif ESP32 Technical Reference Manual page 125

6 DMA Controller (DMA)
6.5 SPI DMA Interface
ESP32 SPI modules can use DMA as well as the CPU for data exchange with peripherals. As can be seen from
Figure 6-4, two DMA channels are shared by SPI1, SPI2 and SPI3 controllers. Each DMA channel can be used
by any one SPI controller at any given time.
The ESP32 SPI DMA Engine also uses a linked list to receive/transmit data. Burst transmission is supported. The
data size for a single transfer must be four bytes aligned. Consecutive data transfer is also supported.
SPI1_DMA_CHAN_SEL[1:0], SPI2_DMA_CHAN_SEL[1:0] and SPI3_DMA_CHAN_SEL[1:0] in DPORT_SPI_DMA_
CHAN_SEL_REG must be configured to enable the SPI DMA interface for a specific SPI controller. Each SPI
controller corresponds to one domain which has two bits with values 0, 1 and 2. Value 3 is reserved and must
not be configured for operation.
Considering SPI1 as an example,
if SPI SPI1_DMA_CHAN_SEL[1:0] = 0, then SPI1 does not use any DMA channel;
if SPI1_DMA_CHAN_SEL[1:0] = 1, then SPI1 enables DMA channel1;
if SPI1_DMA_CHAN_SEL[1:0] = 2, then SPI1 enables DMA channel2.
The SPI_OUTLINK_START bit in SPI_DMA_OUT_LINK_REG and the SPI_INLINK_START bit in SPI_DMA_IN_LINK_REG
are used for enabling the DMA Engine. The two bits are self-cleared by hardware. When SPI_OUTLINK_START
is set to 1, the DMA Engine starts processing the outbound linked list descriptor and prepares to transmit data.
When SPI_INLINK_START is set to 1, then the DMA Engine starts processing the inbound linked-list descriptor
and gets prepared to receive data.
Software should configure the SPI DMA as follows:
1. Reset the DMA state machine and FIFO parameters;
2. Configure the DMA-related registers for operation;
3. Configure the SPI-controller-related registers accordingly;
4. Set SPI_USR to enable DMA operation.
Espressif Systems
Figure 6-4. SPI DMA
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