Espressif ESP32 Technical Reference Manual page 620

27 Memory Management and Protection Units (MMU, MPU)
is a special mode to allow processes with a PID of 2 to 7 to read the External Flash via address V Addr
When the DPORT_PRO_SINGLE_IRAM_ENA bit of register DPORT_PRO_CACHE_CTRL_REG is 1, the MMU enters
this special mode for PRO_CPU memory accesses. Similarily, when the DPORT_APP_SINGLE_IRAM_ENA bit of
register DPORT_APP_CACHE_CTRL_REG is 1, the APP_CPU accesses memory using this special mode. In this
mode, the process and virtual address page supported by each configuration entry of MMU are different. For
details please see Table
cannot be used to access External Flash.
Table 27-12. MMU Entry Numbers for PRO_CPU (Special Mode)
VAddr Count
64
V Addr
0
64
V Addr
1
64
V Addr
2
64
V Addr
3
16
V Addr
4
Table 27-13. MMU Entry Numbers for APP_CPU (Special Mode)
VAddr Count
64
V Addr
0
64
V Addr
1
64
V Addr
2
64
V Addr
3
16
V Addr
4
Every configuration entry of MMU maps a virtual address page of a CPU process to a physical address page. An
entry is 32 bits wide. Of these, bits 0~7 indicate the physical page the virtual page is mapped to. Bit 8 should
be cleared to indicate that the MMU entry is valid; entries with this bit set will not map any physical address to
the virtual address. Bits 10 to 32 are unused and should be written as zero. Because there are eight address
bits in an MMU entry, and the page size for external flash is 64 KB, a maximum of 256 * 64 KB = 16 MB of external
flash is supported.
Examples
Example 1. A PRO_CPU process, with a PID of 1, needs to read external flash address 0x07_2375 via virtual
address 0x3F70_2375. The MMU is not in the special mode.
• According to Table 27-9, virtual address 0x3F70_2375 resides in the 0x30'th page of V Addr
• According to Table 27-10, the MMU entry for V Addr
• The modified MMU entry is 0 + 0x30 = 0x30.
• Address 0x07_2375 resides in the 7'th 64 KB-sized page.
• MMU entry 0x30 needs to be set to 7 and marked as valid by setting the 8'th bit to 0. Thus, 0x007 is
written to MMU entry 0x30.
Espressif Systems
27-12 and 27-13. As shown in these tables, in this special mode V Addr
0/1 2
0 -
64 256
- -
- -
- 1056
0/1 2
2048 -
2112 2304
- -
- -
- 3104
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First MMU entry for PID
3 4
- -
384 512
- -
- -
1072 1088
First MMU entry for PID
3 4
- -
2432 2560
- -
- -
3120 3136
for PID 0/1 for the PRO_CPU starts at 0.
0
620
and V Addr
2
5 6 7
- - -
640 768 896
- - -
- - -
1104 1120 1136
5 6 7
- - -
2688 2816 2944
- - -
- - -
3152 3168 3184
.
0
ESP32 TRM (Version 5.2)
.
1
3