Espressif ESP32 Technical Reference Manual page 444

16 Motor Control PWM (PWM)
Rising edge (RED) and falling edge (FED) delays may be set up independently. The delay value is programmed
using the 16-bit registers
clock (DT_clk) periods by which a signal edge is delayed. DT_CLK can be selected from PWM_clk or PT_clk
through register PWM_DTx_CLK_SEL.
To calculate the delay on falling edge (FED) and rising edge (RED), use the following formulas:
Espressif Systems
Figure 16-26. Active Low (AL) Dead Time Waveforms
PWM_DTx_RED and PWM_DTx_FED. The register value represents the number of
F ED = P W M _DT x_F ED × T
RED = P W M _DT x_RED × T
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DT _clk
DT _clk
444 ESP32 TRM (Version 5.2)