Espressif ESP32 Technical Reference Manual page 104

5 DPort Registers
31
0 0 0 0 0 0 0
DPORT_PERI_RST_RSA Set the bit to reset RSA module. Clear the bit to release RSA module. (R/W)
DPORT_PERI_RST_SHA Set the bit to reset SHA module. Clear the bit to release SHA module. (R/W)
DPORT_PERI_RST_AES Set the bit to reset AES module. Clear the bit to release AES module. (R/W)
31
0 0 0 0 0 0 0
DPORT_APPCPU_RESETTING Set to 1 to reset APP_CPU. Clear the bit to release APP_CPU. (R/W)
31
0 0 0 0 0 0 0
DPORT_APPCPU_CLKGATE_EN Set to 1 to enable the clock of APP_CPU. Clear the bit to disable
the clock of APP_CPU. (R/W)
Espressif Systems
Register 5.4. DPORT_PERI_RST_EN_REG (0x020)
0 0 0 0 0 0 0 0
Register 5.5. DPORT_APPCPU_CTRL_REG_A_REG (0x02C)
0 0 0 0 0 0 0 0
Register 5.6. DPORT_APPCPU_CTRL_REG_B_REG (0x030)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
104
3 2
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
1 0
0
Reset
1 0
0 1
Reset
1 0
0 0
Reset