Espressif ESP32 Technical Reference Manual page 701

31 Low-Power Management (RTC_CNTL)
All the wakeup sources specified in Table
sleep.
Users can configure the reject to sleep option via the following registers.
• Configure the
RTC_CNTL_SLP_REJECT
– Set RTC_CNTL_LIGHT_SLP_REJECT_EN
– Set RTC_CNTL_DEEP_SLP_REJECT_EN
• Read
RTC_CNTL_REJECT_CAUSE
31.3.12 RTC Timer
The RTC timer is a 48-bit counter that can be read. The clock is RTC_SLOW_CLK. Any reset/sleep mode, except
for the power-up reset, will not stop or reset the RTC timer.
The RTC timer can be used to wake up the CPU at a designated time, and to wake up TOUCH or the ULP
coprocessor periodically.
31.3.13 RTC Boot
Since the CPU, ROM and RAM are powered down during Deep-sleep and Hibernation mode, the wake-up time is
much longer than that in Light sleep/Modem sleep, because of the ROM unpacking and data-copying from the
flash (SPI booting). There are two types of SRAM in the RTC, named slow RTC memory and fast RTC memory,
which remain powered-on in Deep-sleep mode. For small-scale codes (less than 8 KB), there are two methods
of speeding up the wake-up time, i.e. avoiding ROM unpacking and SPI booting.
The first method is to use the RTC slow memory:
1. Set register RTC_CNTL_PROCPU_STAT_VECTOR_SEL
for APP_CPU) to 0.
2. Put the chip into sleep.
3. When the CPU is powered up, the reset vector starts from 0x50000000, instead of 0x40000400. ROM
unpacking & SPI boot are not needed. The code in RTC memory has to do itself some initialization for the
C program environment.
The second method is to use the fast RTC memory:
1. Set register RTC_CNTL_PROCPU_STAT_VECTOR_SEL
for APP_CPU) to 1.
2. Calculate CRC for the fast RTC memory, and save the result in register RTC_CNTL_RTC_STORE6_REG[31:0].
3. Input register RTC_CNTL_RTC_STORE7_REG[31:0]
4. Put the chip into sleep.
5. When the CPU is powered up, after ROM unpacking and some necessary initialization, the CRC is calcu-
lated again. If the result matches with register RTC_CNTL_RTC_STORE6_REG[31:0], the CPU will jump to
the entry address.
The boot flow is shown in Figure 31-11.
Espressif Systems
31-2 (except UART) can also be configured as the causes to reject
field to enable or disable the option to reject to sleep:
to enable reject-to-light-sleep.
to enable reject-to-deep-sleep.
to check the reason for rejecting to sleep.
for PRO_CPU (or register
for PRO_CPU (or register
with the entry address in the fast RTC memory.
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RTC_CNTL_APPCPU_STAT_VECTOR_SEL
RTC_CNTL_APPCPU_STAT_VECTOR_SEL
ESP32 TRM (Version 5.2)