Espressif ESP32 Technical Reference Manual page 288

10 Ethernet Media Access Controller (MAC)
31
0 0 0 0 0 0 0
EMAC_PHY_INTF_SEL The PHY interface selected. 0x0: PHY MII, 0x4: PHY RMII. (R/W)
31
0 0 0 0 0 0 0
EMAC_RAM_PD_EN Ethernet RAM power-down enable signal. Bit[0]: TX SRAM; Bit[1]: RX SRAM.
Setting the bit to 1 powers down the RAM. (R/W)
Espressif Systems
Register 10.47. EMAC_EX_PHYINF_CONF_REG (0x080C)
0 0 0 0 0 0 0 0
Register 10.48. EMAC_PD_SEL_REG (0x0810)
0 0 0 0 0 0 0 0
Submit Documentation Feedback
16 15 13 12
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
288
0 0 0 0 0 0 0 0
2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
Reset