Espressif ESP32 Technical Reference Manual page 34

1 System and Memory
1.3.5.2 Non-Contiguous Peripheral Memory Ranges
The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~
3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU's data bus. Similarly to other peripherals, access to
this peripheral is identical for both CPUs.
1.3.5.3 Memory Speed
The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single cycle.
The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the FAST_CLOCK, so
access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.
Espressif Systems 34 ESP32 TRM (Version 5.2)
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