Espressif ESP32 Technical Reference Manual page 114

5 DPort Registers
31
0 0 0 0 0 0 0
DPORT_EMAC_RST Set the bit to reset Ethernet MAC module. Clear the bit to release Ethernet MAC
module. (R/W)
DPORT_SDIO_HOST_RST Set the bit to reset SD/MMC module. Clear the bit to release SD/MMC
module. (R/W)
DPORT_SDIO_RST Set the bit to reset SDIO module. Clear the bit to release SDIO module. (R/W)
Register 5.23. DPORT_CPU_INTR_FROM_CPU_n_REG (n: 0-3) (0xDC+4*n)
31
0 0 0 0 0 0 0
DPORT_CPU_INTR_FROM_CPU_n
Register 5.24. DPORT_PRO_INTR_STATUS_REG_n_REG (n: 0-2) (0xEC+4*n)
31
DPORT_PRO_INTR_STATUS_REG_n_REG PRO_CPU interrupt status. (RO)
Register 5.25. DPORT_APP_INTR_STATUS_REG_n_REG (n: 0-2) (0xF8+4*n)
31
DPORT_APP_INTR_STATUS_REG_n_REG APP_CPU interrupt status. (RO)
Espressif Systems
Register 5.22. DPORT_WIFI_RST_EN_REG (0x0D0)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Interrupt in both CPUs. (R/W)
0x000000000
0x000000000
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0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
114
8 7 6 5 4
0 0 0 0 0 0 0 0
1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0 Reset
0
0 Reset
0
Reset
0
Reset