Espressif ESP32 Technical Reference Manual page 225

9 SD/MMC Host Controller
31
BUFADDR_REG Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
reset. This register points to the current Data Buffer Address being accessed by the IDMAC.
(RO)
31
0x000
CCLKIN_EDGE_N This value should be equal to CCLKIN_EDGE_L. (R/W)
CCLKIN_EDGE_L The low level of the divider clock.
CCLKIN_EDGE_H. (R/W)
CCLKIN_EDGE_H The high level of the divider clock.
CCLKIN_EDGE_L. (R/W)
CCLKIN_EDGE_SLF_SEL It is used to select the clock phase of the internal signal from phase90,
phase180, or phase270. (R/W)
CCLKIN_EDGE_SAM_SEL It is used to select the clock phase of the input signal from phase90,
phase180, or phase270. (R/W)
CCLKIN_EDGE_DRV_SEL It is used to select the clock phase of the output signal from phase90,
phase180, or phase270. (R/W)
Espressif Systems
Register 9.33. BUFADDR_REG (0x0098)
0x000000000
Register 9.34. CLK_EDGE_SEL (0x0800)
21 20 17 16
0x1 0x0
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13 12 9 8 6
0x1 0x0
The value should be larger than
The value should be smaller than
0
Reset
5 3 2 0
0x0 0x0
Reset
ESP32 TRM (Version 5.2)