Espressif ESP32 Technical Reference Manual page 618

27 Memory Management and Protection Units (MMU, MPU)
Size
Low
8 KB 0x3FFE_8000
8 KB 0x3FFE_A000
8 KB 0x3FFE_C000
8 KB 0x3FFE_E000
8 KB 0x3FFF_0000
8 KB 0x3FFF_2000
8 KB 0x3FFF_4000
8 KB 0x3FFF_6000
8 KB 0x3FFF_8000
8 KB 0x3FFF_A000
8 KB 0x3FFF_C000
8 KB 0x3FFF_E000
Registers DPROT_AHB_MPU_TABLE_0_REG and DPROT_AHB_MPU_TABLE_1_REG are located in the DPort ad-
dress space. Only processes with a PID of 0 or 1 can modify these two registers.
Note:
In hardware, there are three instruction buses corresponding to V Addr
three buses can initiate load or fetch accesses simultaneously, but only one access is true. If more than one unmasked
instruction buses are present, then bit8 of all MMU entries should be set to zero. Otherwise, when an invalid MMU
entry is used by an access, the cache will be stalled even if there is no program at this access.
27.3.2.2 External Memory
Accesses to the external flash and external SPI RAM are done through a cache and are also handled by an MMU.
This Cache MMU can apply different mappings, depending on the PID of the process as well as the CPU the
process is running on. The MMU does this in a way that is similar to the internal memory MMU, that is, for every
page of virtual memory, it has a register detailing which physical page this virtual page should map to. There are
differences between the MMUs governing the internal memory and the Cache MMU, though. First of all, the
Cache MMU has a fixed page size (which is 64 KB for external flash and 32 KB for external RAM) and secondly,
instead of specifying access rights in the MMU entries, the Cache MMU has explicit mapping tables for each
PID and processor core. The MMU mapping configuration registers will be referred to as 'entries' in the rest of
this chapter. These registers are only accessible from processes with a PID of 0 or 1; processes with a PID of 2
to 7 will have to delegate to one of the above-mentioned processes to change their MMU settings.
The MMU entries, as stated before, are used for mapping a virtual memory page access to a physical memory
page access. The MMU controls five regions of virtual address space, detailed in Table 27-9. V Addr
are used for accessing external flash, whereas V Addr
V Addr
4
that V Addr is a subset of V Addr
4
Espressif Systems
Boundary address
High
0x3FFE_9FFF
0x3FFE_BFFF
0x3FFE_DFFF
0x3FFE_FFFF
0x3FFF_1FFF
0x3FFF_3FFF
0x3FFF_5FFF
0x3FFF_7FFF
0x3FFF_9FFF
0x3FFF_BFFF
0x3FFF_DFFF
0x3FFF_FFFF
.
0
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Register
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
DPORT_AHB_MPU_TABLE_1_REG
, V Addr , and V Addr
1 2
is used for accessing external RAM. Note
RAM
618
Authority
Bit
29
30
31
0
1
2
3
4
5
6
7
8
, respectively. These
3
ESP32 TRM (Version 5.2)
to
1