24 RSA Accelerator (RSA)
the result Z. X is left-extended and Y is right-extended, and defined as follows:
ˆ X = ( ˆ X
ˆ Y = ( ˆ Y
Software performs the operation in the following order:
ˆ N
1. Write (
1 + 8) to RSA_MULT_MODE_REG.
512
2. Write ˆ X
and ˆ Y
(i ∈ [0, ˆ n ) ∩ N) to RSA_X_MEM and RSA_Z_MEM, respectively.
i
i
Write the valid data into each number's memory block, according to their lengths. Values beyond this
length are ignored. Half of the base-b positional notations written to the memory are zero (using the
derivations shown above). These zero values are indispensable.
3. Write 1 to RSA_MULT_START_REG.
4. Wait for the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR
interrupt is generated.
5. Read the result Z
i
6. Write 1 to RSA_INTERRUPT_REG to clear the interrupt.
After the operation, only the RSA_MULT_MODE_REG register remains unmodified.
24.4 Register Summary
Name
Configuration registers
RSA_M_PRIME_REG
Modular exponentiation registers
RSA_MODEXP_MODE_REG
RSA_MODEXP_START_REG
Modular multiplication registers
RSA_MULT_MODE_REG
RSA_MULT_START_REG
Misc registers
RSA_INTERRUPT_REG
RSA_CLEAN_REG
Espressif Systems
ˆ X
· · · ˆ X
= (00 · · · 0
)
ˆ n 1
ˆ n 2
0
b
ˆ Y
· · · ˆ Y
= (Y 00 · · · 0
)
ˆ n 1
ˆ n 2
0
b
(i ∈ [0, ˆ n ) ∩ N) from RSA_Z_MEM.
Description
Register to store M'
Modular exponentiation mode
Start bit
Modular multiplication mode
Start bit
RSA interrupt register
RSA clean register
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N
n =
32
ˆ N = 2 × N
ˆ N
ˆ n =
= 2n
32
= (00 · · · 0
X)
X
b
n
n
)
= (Y
Y
b
n 1
n 2
n
601
· · · X
X
)
n 1
n 2
0
b
· · · Y
00 · · · 0
)
0
b
n
Address
0x3FF02800
0x3FF02804
0x3FF02808
0x3FF0280C
0x3FF02810
0x3FF02814
0x3FF02818
ESP32 TRM (Version 5.2)
Access
R/W
R/W
WO
R/W
WO
R/W
RO
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