Espressif ESP32 Technical Reference Manual page 466

16 Motor Control PWM (PWM)
31
0 0 0 0 0 0 0
PWM_DT0_CLK_SEL Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk. (R/W)
PWM_DT0_B_OUTBYPASS S0 in Table 16-5. (R/W)
PWM_DT0_A_OUTBYPASS S1 in Table 16-5. (R/W)
PWM_DT0_FED_OUTINVERT S3 in Table 16-5. (R/W)
PWM_DT0_RED_OUTINVERT S2 in Table 16-5. (R/W)
PWM_DT0_FED_INSEL S5 in Table 16-5. (R/W)
PWM_DT0_RED_INSEL S4 in Table 16-5. (R/W)
PWM_DT0_B_OUTSWAP S7 in Table 16-5. (R/W)
PWM_DT0_A_OUTSWAP S6 in Table 16-5. (R/W)
PWM_DT0_DEB_MODE S8 in Table 16-5, dual-edge B mode. 0: FED/RED take effect on different
paths separately, 1: FED/RED take effect on B path. (R/W)
PWM_DT0_RED_UPMETHOD Updating method for RED (rising edge delay) active register. 0: im-
mediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when
bit3 is set to 1: disable the update. (R/W)
PWM_DT0_FED_UPMETHOD Updating method for FED (falling edge delay) active register. 0: im-
mediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when
bit3 is set to 1: disable the update. (R/W)
31
0 0 0 0 0 0 0
PWM_DT0_FED Shadow register for FED. (R/W)
Espressif Systems
Register 16.23. PWM_DT0_CFG_REG (0x0058)
18 17
0 0 0 0 0 0 0 0
Register 16.24. PWM_DT0_FED_CFG_REG (0x005c)
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
1 1 0 0 0 0 0 0
16 15
0
466
8 7 4 3
0 0 0
0
ESP32 TRM (Version 5.2)
0
Reset
0
Reset