Espressif ESP32 Technical Reference Manual page 260

10 Ethernet Media Access Controller (MAC)
31
0 0 0 0 0 0 0
DMAIN_NISE When this bit is set, normal interrupt summary is enabled. When this bit is reset,
normal interrupt summary is disabled. This bit enables the following interrupts in Status Register:
(R/W)
• Bit[0]: Transmit Interrupt.
• Bit[2]: Transmit Buffer Unavailable.
• Bit[6]: Receive Interrupt.
• Bit[14]: Early Receive Interrupt.
DMAIN_AISE When this bit is set, abnormal interrupt summary is enabled. When this bit is reset,
the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status
Register:(R/W)
• Bit[1]: Transmit Process Stopped.
• Bit[3]: Transmit Jabber Timeout.
• Bit[4]: Receive Overflow.
• Bit[5]: Transmit Underflow.
• Bit[7]: Receive Buffer Unavailable.
• Bit[8]: Receive Process Stopped.
• Bit[9]: Receive Watchdog Timeout.
• Bit[10]: Early Transmit Interrupt.
• Bit[13]: Fatal Bus Error.
DMAIN_ERIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Early Receive
Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. (R/W)
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Espressif Systems
Register 10.8. DMAIN_EN_REG (0x001C)
17
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
260
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset