Espressif ESP32 Technical Reference Manual page 726

31 Low-Power Management (RTC_CNTL)
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RTC_CNTL_REG_RTC_CNTL_DG_PAD_AUTOHOLD_EN Digital pad enable auto-hold. (R/W)
RTC_CNTL_CLR_REG_RTC_CNTL_DG_PAD_AUTOHOLD Write-only register clears digital pad auto-
hold. (WO)
RTC_CNTL_DG_PAD_AUTOHOLD Read-only register indicates digital pad auto-hold status. (RO)
31 30 28 27 25
0 0 0
RTC_CNTL_WDT_PAUSE_IN_SLP Pause RTC WDT in sleep. (R/W)
RTC_CNTL_WDT_APPCPU_RESET_EN RTC WDT reset APP_CPU enable. (R/W)
RTC_CNTL_WDT_PROCPU_RESET_EN RTC WDT reset PRO_CPU enable. (R/W)
RTC_CNTL_WDT_FLASHBOOT_MOD_EN Enable RTC WDT in flash boot. (R/W)
RTC_CNTL_WDT_SYS_RESET_LENGTH System reset counter length, unit: RTC_SLOW_CLK cycle.
The value can be 0 ~ 7. (R/W)
RTC_CNTL_WDT_CPU_RESET_LENGTH CPU reset counter length, unit: RTC_SLOW_CLK cycle.
The value can be 0 ~ 7. (R/W)
RTC_CNTL_WDT_STG3 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)
RTC_CNTL_WDT_STG2 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)
RTC_CNTL_WDT_STG1 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)
RTC_CNTL_WDT_STG0 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage
enable, 4: RTC reset stage enable. (R/W)
RTC_CNTL_WDT_EN Enable RTC WDT. (R/W)
Espressif Systems
Register 31.29. RTC_CNTL_DIG_ISO_REG (0x0088)
Register 31.30. RTC_CNTL_WDTCONFIG0_REG (0x008C)
24 22 21 19 18 17
0 0 0 0
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16 14 13 11 10 9
1 1 1 0
726
8 7 6
0 1 0
ESP32 TRM (Version 5.2)
0
Reset